數字電路設計@heyian910

verilog數字電路實驗交通燈

源碼

module main(
		input clk,
		input clr,
		input start,
		input stopa,
		input stopb,
		input pause,
		output [3:0] AN,
		output [7:0] SEG,
		output reg [2:0] LA,LB//紅 黃 綠
    );
	 reg [1:0] state1,state2;
	 reg newstart = 1'b1;  //
	 reg [15:0] Data;
	 reg [3:0] Data_4;
	 wire [1:0] BIT_SEL;
	 reg Increment;
	 integer clk_num=0;
	 delay_5ms uu1(clk,BIT_SEL);
	 SMG uu2(Data_4,BIT_SEL,SEG,AN);
	 
	 initial begin Data <= 16'b0; Increment = 1'b0;end
	 
	 always@(posedge clk)
	 begin
		if(clk_num<25000000) //設定數字跳轉頻率
		begin
			clk_num = clk_num+1;
			Increment = 1'b0;
		end
		else
		begin
			clk_num = 0;
			Increment = 1'b1;
		end
	 end
	 
always@(posedge clr  or posedge Increment )
if(clr)
begin
   Data <= 16'b1010101010101010;//輸出“----”
	LA <= 3'b100;
	LB <= 3'b100;
	state1 <= 2'b00;
	state2 <= 2'b00;
	newstart = 1'b1;
end		
else if(stopa)
     begin
		 Data <= 16'b1111111111111111;//熄滅
		 LA <= 3'b100;
		 LB <= 3'b001;
	  end
	  else if(stopb)
	       begin
		      Data <= 16'b1111111111111111;//熄滅
		      LA <= 3'b001;
		      LB <= 3'b100;
	       end
	       else if(start)                      //系統開始運作
	            begin
		           if(!pause)
		           begin
			          if(newstart==1'b1)
			          begin
				         Data <=16'b0010000000110000;//30s 40s          111111111111111111111111
				         LA<=3'b001; //主綠 
				         LB<=3'b100;  //次紅
				         newstart = 1'b0;
			          end
			          if(Data[3:0]==4'b0000)  //次道次位為0
			          begin
				         if(Data[7:4]==4'b0000)
				         begin
					        if(state2==2'b00)
					        begin
						       state2<=2'b01;
						       Data[7:0]<=8'b00010101;//15s            33333333333333333333333333
						       LB<=3'b001; //次綠
					        end
					        else if(state2==2'b01)
					             begin
						            state2<=2'b10;
						            Data[7:0]<=8'b0000101;//5s               4444444444444444444444444
						            LB<=3'b010; //次黃
					             end
					             else if(state2==2'b10)
					                  begin
						                 state2 <= 2'b00;
						                 Data[7:0]<=8'b01000000;//40s
						                 LB<=3'b100;  //次紅·
					                  end
				         end
				         else
				         begin
					        Data[3:0]<=4'b1001;
					        Data[7:4]<=Data[7:4]-4'b0001;
				         end
			          end	
			          else
						 begin
				         Data[3:0]<=Data[3:0]-4'b0001;
						 end
			          if(Data[11:8]==4'b0000) //主道次位為0
			          begin
				         if(Data[15:12]==4'b0000)
				         begin
					        if(state1==2'b00)
					        begin
						       state1<=2'b01;
						       Data[15:8]<=8'b00010000;//10s             2222222222222222222222222
						       LA<=3'b010; //主黃
					        end
					        else if(state1==2'b01)
					             begin
						            state1<=2'b10;
						            Data[15:8] <=8'b00100000;//20s            3333333333333333333333333
						            LA<=3'b100; //主紅
					             end
					             else if(state1==2'b10)
					                  begin
						                 state1 <= 2'b00;
						                 Data[15:8] <=8'b00110000;//30s
						                 LA<=3'b001; //主綠
					                  end
				         end
				         else
				         begin
					        Data[11:8]<=4'b1001;
					        Data[15:12]<=Data[15:12]-4'b0001;
				         end
			          end
			          else
						 begin
				         Data[11:8]<=Data[11:8]-4'b0001;
						 end
			        end
               end

always @(*)	// case（BIT_SEL）控制每個數位管顯示對應位的數字
	  //根據BIT_SEL，将要顯示的4位十六進制數賦給Data_4
	  begin
			case(BIT_SEL)
				2'b00:Data_4[3:0]<=Data[15:12];
				2'b01:Data_4[3:0]<=Data[11:8];
				2'b10:Data_4[3:0]<=Data[7:4];
				2'b11:Data_4[3:0]<=Data[3:0];
				default:Data_4[3:0]<=Data[3:0];
			endcase
	  end
endmodule

module delay_5ms(clk,BIT_SEL);
	input clk;
	output reg[1:0] BIT_SEL;
	integer cnt=0;
	initial begin BIT_SEL <= 2'b00;end
	always@(posedge clk)
	begin
				cnt<=cnt+1;
				if(cnt>50000)
				begin
					BIT_SEL<=BIT_SEL+2'b01;
					cnt<=0;
				end
	end
endmodule

module SMG(
		input wire[3:0] data,		 //要顯示的數字
      input wire[1:0] bit_sel,    //數位管選擇，00~11 最左到最右
      output reg[7:0] seg,		    //段選
      output reg[3:0] AN			 //位選
);
	always @(*)
		begin
			case(bit_sel)
				2'b00:AN<=4'b1000;
				2'b01:AN<=4'b1001;
				2'b10:AN<=4'b1010;
				2'b11:AN<=4'b1011;
				default:AN<=4'b1111;
			endcase
		end
	always @(*)
		begin
			case(data[3:0])
				4'b0000:seg[7:0]<=8'b00000011;
				4'b0001:seg[7:0]<=8'b10011111;
				4'b0010:seg[7:0]<=8'b00100101;
				4'b0011:seg[7:0]<=8'b00001101;
				4'b0100:seg[7:0]<=8'b10011001;
				4'b0101:seg[7:0]<=8'b01001001;
				4'b0110:seg[7:0]<=8'b01000001;
				4'b0111:seg[7:0]<=8'b00011111;
				4'b1000:seg[7:0]<=8'b00000001;
				4'b1001:seg[7:0]<=8'b00001001;
				4'b1010:seg[7:0]<=8'b10111111;
				default:seg[7:0]<=8'b11111111;
			endcase
		end
endmodule

測試樣例（激勵檔案）

initial begin
		// Initialize Inputs
		clk = 0;
		clr = 0;
		start = 0;
		stopa = 0;
		stopb = 0;
		pause = 0;
        #100;
		// Wait 100 ns for global reset to finish
		
        
		// Add stimulus here
		clr=1;
		#50;
		
		clr=0;
		start=1;
	 end
      always
		begin
			clk = ~clk;
			#50;
		end
endmodule

進行仿真的時候建議将源碼中的clk_num和cnt所需滿足的條件改小，然後讓仿真波形圖多跑一會

管腳配置

NET "AN[3]" LOC = L21;
NET "AN[3]" IOSTANDARD = LVCMOS18;
NET "AN[2]" LOC = M22;
NET "AN[2]" IOSTANDARD = LVCMOS18;
NET "AN[1]" LOC = M21;
NET "AN[1]" IOSTANDARD = LVCMOS18;
NET "AN[0]" LOC = N22;
NET "AN[0]" IOSTANDARD = LVCMOS18;
NET "SEG[7]" LOC = H19;
NET "SEG[7]" IOSTANDARD = LVCMOS18;
NET "SEG[6]" LOC = G20;
NET "SEG[6]" IOSTANDARD = LVCMOS18;
NET "SEG[5]" LOC = J22;
NET "SEG[5]" IOSTANDARD = LVCMOS18;
NET "SEG[4]" LOC = K22;
NET "SEG[4]" IOSTANDARD = LVCMOS18;
NET "SEG[3]" LOC = K21;
NET "SEG[3]" IOSTANDARD = LVCMOS18;
NET "SEG[2]" LOC = H20;
NET "SEG[2]" IOSTANDARD = LVCMOS18;
NET "SEG[1]" LOC = H22;
NET "SEG[1]" IOSTANDARD = LVCMOS18;
NET "SEG[0]" LOC = J21;
NET "SEG[0]" IOSTANDARD = LVCMOS18;
NET "clk" IOSTANDARD = LVCMOS18;
NET "clk" LOC = H4;

# PlanAhead Generated IO constraints 

NET "LB[2]" IOSTANDARD = LVCMOS18;
NET "LB[1]" IOSTANDARD = LVCMOS18;
NET "LB[0]" IOSTANDARD = LVCMOS18;
NET "LA[2]" IOSTANDARD = LVCMOS18;
NET "LA[1]" IOSTANDARD = LVCMOS18;
NET "LA[0]" IOSTANDARD = LVCMOS18;
NET "clr" IOSTANDARD = LVCMOS18;
NET "pause" IOSTANDARD = LVCMOS18;
NET "start" IOSTANDARD = LVCMOS18;
NET "stopa" IOSTANDARD = LVCMOS18;
NET "stopb" IOSTANDARD = LVCMOS18;

# PlanAhead Generated physical constraints 

NET "LA[2]" LOC = R1;
NET "LA[1]" LOC = P2;
NET "LA[0]" LOC = P1;
NET "LB[2]" LOC = N2;
NET "LB[1]" LOC = M1;
NET "LB[0]" LOC = M2;
NET "pause" LOC = R4;
NET "clr" LOC = T3;
NET "start" LOC = U3;
NET "stopa" LOC = T4;
NET "stopb" LOC = V3;

# PlanAhead Generated IO constraints 

NET "clk" PULLDOWN;
NET "clr" PULLDOWN;
NET "pause" PULLDOWN;
NET "start" PULLDOWN;
NET "stopa" PULLDOWN;
NET "stopb" PULLDOWN;

verilog數字電路實驗交通燈verilog數字電路實驗交通燈

verilog數字電路實驗交通燈

源碼

測試樣例（激勵檔案）

管腳配置

繼續閱讀

基于QuartusII的verilog數字時鐘設計

verilog基礎設計6-台積電數字ic筆試verilog程式設計題

Verilog 數字電路設計之帶hazard的五級流水線CPU

【verilog】淺複習狀态機（FSM）狀态機代碼寫法案例一（簡單可樂機）代碼以及輸出案例二（可以找零的可樂機）

2021-08-21Verilog三段式狀态機的寫法，标準示例和仿真。

verilog實作Lemmings（瘋狂小旅鼠）遊戲Lemmings1Lemmings2Lemmings3Lemmings4

異步複位同步釋放(Asynchronous Reset Synchronous Release)

數字IC秋招手撕代碼（六）異步FIFO

數字IC秋招手撕代碼（五）脈沖檢測題目分析代碼

數字IC秋招手撕代碼（四）同步FIFO實作題目分析代碼

數字IC秋招手撕代碼（一）異步雙端口ram題目設計思路代碼

用卡諾圖進行數字邏輯化簡

初學Zynq與Vivado

關于格雷碼格雷碼的特點：轉換方法

關于U-BOOT，以及ZYNQ7啟動檔案的對話記錄。

1.5v下的10位ADC設計舉例

verilog數字電路實驗 交通燈verilog數字電路實驗 交通燈

verilog數字電路實驗 交通燈

源碼

測試樣例（激勵檔案）

管腳配置

繼續閱讀

verilog數字電路實驗交通燈verilog數字電路實驗交通燈

verilog數字電路實驗交通燈