這裡綜合了Altera提供的各種文獻和執行個體，在最新的Quartus 13.1建構。
1. New Project
2.Create New System
Ctrl+R，将時鐘Name更改為clk_50，頻率為50MHz
加入altpll元件，c0->100MHz，作為系統時鐘；c1->100MHz，相位延遲-2ns，作為SDRAM時鐘；C2->10MHz，作為其他LCD，LED等時鐘；可選C3->65MHz，作為VGA像素時鐘。（圖就不改了）
在View菜單中，打開Clocks視圖，修改時鐘名字提高易讀性。分别是altpll_sys, altpll_sdram, altpll_io, altpll_vga。
altpll.inclk_interface設定為clk_50，輕按兩下altpll的export，導出areset，locked，phasedone。這個locked信号可以做nios的reset
加入NIOS Processor，JTAG UART（IRQ 0）
加入SDRAM controller，導出wire，位址鎖定為0x0
各component的clk均為altpll_sys，sdram的Avalon Memory Mapped Slave連接配接到cpu.data_master和instruction_master。
添加Generic Tri-State Controller，作為Common Flash Interface，名字為ext_flash（和web server app模版名字相同）
添加Tri-State Conduit Bridge作為Flash的端口，連接配接ext_flash.uas->cpu.data_master，ext_flash.tcm->tristate_conduit_bridge_flash.tcs，導出tristate_conduit_bridge_flash.out
add Triple-Speed Ethernet，名字為tse_mac（web sever模闆中的名字），Core Variations: 10/10/100Mb Ethernet MAC，Interface RGMII，Include MDIO Module (MDC/MDIO)
terASIC提供的DE2_115_Web_Server.qsys中Triple-Speed Ethernet的名字有錯（13改了名？）。可用文本編輯器修改此qsys檔案，查找triple_speed_ethernet，修改module為：
<module kind="altera_eth_tse" version="13.1" enabled="1" name="tse_mac">
添加On-Chip Memory作為 Descriptor Memory
add scatter-gatter dma controller，Memory To Stream，Source error width為1，作為發送DMA
再次add scatter gather dma controller，Stream To Memory，Sink error width為6
tse, descriptor memory, dma時鐘都是alt_sys。
tse.control_port->cpu.data_master
tse.receive_clock->altpll_sys
tse.transmit_clock->altpll_sys
接收鍊路：tse.receive->sgdma_rx.in, sgdma_rx.m_write->sdram.s1
發送鍊路：sgdma_tx.m_read->sdram.s1, sgdma_tx.out->tse.trnsmit
sgdma_rx, sgdma_tx兩者的descriptor read 和descriptor write，都連接配接到descriptor_memory.s1，->cpu.data_master
sgdma_rx設定irq 2，sgdma_tx設定irq 3
根據提示導出tse的conduits
以上時鐘都适用系統時鐘，mapped slave都連接配接到cpu.data_master上，包括altpll.pll_slave
添加Avalon-MM Clock Crossing Bridge，設定适當深度
clock_crossing_bridge.m0_clk->altpll_io，clock_crossing_bridge.s0_clk->altpll_sys，clock_crossing_bridge.s0->cpu.data_master。
除非特别說明，以下系統的低速裝置都使用altpll_io和clock_crossing_bridge.m0連接配接到clk和mapped slave (s1)。
add Interval Timer (IRQ 1), System ID, LCD 16027, LED pio （led_pio）, SWITCH pio, Seven Segment Display pio, KEY pio (可将KEY[0]留作全局reset)
這裡強調一點：System ID是很重要的一個裝置，設定一個常數，和timestamp配合判斷NIOS和你的BSP是否比對，不要在Run Configuration 中采取 Ignore mismatched system timestamp，我常常因為這個 mismatch 的提示才知道bsp不比對。
修改cpu，reset vector memory 和 exception vector memory 都設定為 sdram.s1
菜單System -> Create Global Reset Network
System -> assign base address
FIle -> Save
應當隻有一個警告
Warning: System.flash: Properties (isFlash,isMemoryDevice,isNonVolatileStorage) have been set on interface uas - in composed mode these are ignored
終于可以：Generate -> Generating...
Generate -> HDL example, copy
3. Create a new DDIO_OUT megafunction variation
width 設定為 1bit，Neither asynchronous clear nor asynchronous set ports options.
4. Create a new altpll megafunction variation
輸入時鐘為以太網的接收時鐘，c0:125MHz; c1: 125MHz, 90deg; c2:125MHz, 180deg
5. New systemverilog file
paste HDL example
從terasic提供的例子中copy端口描述部分
修改nios的執行個體化部分
`define NET0
module web_server(
<span style="white-space:pre"> </span> CLOCK //
<span style="white-space:pre"> </span>CLOCK_50,
CLOCK2_50,
CLOCK3_50,
<span style="white-space:pre"> </span>ENETCLK_25,
<span style="white-space:pre"> </span> Sma //
<span style="white-space:pre"> </span>SMA_CLKIN,
<span style="white-space:pre"> </span>SMA_CLKOUT,
<span style="white-space:pre"> </span> LED //
<span style="white-space:pre"> </span>LEDG,
<span style="white-space:pre"> </span>LEDR,
<span style="white-space:pre"> </span> KEY //
<span style="white-space:pre"> </span>KEY,
<span style="white-space:pre"> </span> SW //
<span style="white-space:pre"> </span>SW,
<span style="white-space:pre"> </span> SEG7 //
<span style="white-space:pre"> </span>HEX0,
<span style="white-space:pre"> </span>HEX1,
<span style="white-space:pre"> </span>HEX2,
<span style="white-space:pre"> </span>HEX3,
<span style="white-space:pre"> </span>HEX4,
<span style="white-space:pre"> </span>HEX5,
<span style="white-space:pre"> </span>HEX6,
<span style="white-space:pre"> </span>HEX7,
<span style="white-space:pre"> </span> LCD //
<span style="white-space:pre"> </span>LCD_BLON,
<span style="white-space:pre"> </span>LCD_DATA,
<span style="white-space:pre"> </span>LCD_EN,
<span style="white-space:pre"> </span>LCD_ON,
<span style="white-space:pre"> </span>LCD_RS,
<span style="white-space:pre"> </span>LCD_RW,
<span style="white-space:pre"> </span> RS232 //
<span style="white-space:pre"> </span>UART_CTS,
<span style="white-space:pre"> </span>UART_RTS,
<span style="white-space:pre"> </span>UART_RXD,
<span style="white-space:pre"> </span>UART_TXD,
<span style="white-space:pre"> </span> PS2 //
<span style="white-space:pre"> </span>PS2_CLK,
<span style="white-space:pre"> </span>PS2_DAT,
<span style="white-space:pre"> </span>PS2_CLK2,
<span style="white-space:pre"> </span>PS2_DAT2,
<span style="white-space:pre"> </span> SDCARD //
<span style="white-space:pre"> </span>SD_CLK,
<span style="white-space:pre"> </span>SD_CMD,
<span style="white-space:pre"> </span>SD_DAT,
<span style="white-space:pre"> </span>SD_WP_N,
<span style="white-space:pre"> </span> VGA //
<span style="white-space:pre"> </span>VGA_B,
<span style="white-space:pre"> </span>VGA_BLANK_N,
<span style="white-space:pre"> </span>VGA_CLK,
<span style="white-space:pre"> </span>VGA_G,
<span style="white-space:pre"> </span>VGA_HS,
<span style="white-space:pre"> </span>VGA_R,
<span style="white-space:pre"> </span>VGA_SYNC_N,
<span style="white-space:pre"> </span>VGA_VS,
<span style="white-space:pre"> </span> Audio //
<span style="white-space:pre"> </span>AUD_ADCDAT,
<span style="white-space:pre"> </span>AUD_ADCLRCK,
<span style="white-space:pre"> </span>AUD_BCLK,
<span style="white-space:pre"> </span>AUD_DACDAT,
<span style="white-space:pre"> </span>AUD_DACLRCK,
<span style="white-space:pre"> </span>AUD_XCK,
<span style="white-space:pre"> </span> I2C for EEPROM //
<span style="white-space:pre"> </span>EEP_I2C_SCLK,
<span style="white-space:pre"> </span>EEP_I2C_SDAT,
<span style="white-space:pre"> </span> I2C for Audio and Tv-Decode //
<span style="white-space:pre"> </span>I2C_SCLK,
<span style="white-space:pre"> </span>I2C_SDAT,
<span style="white-space:pre"> </span> Ethernet 0 //
<span style="white-space:pre"> </span>ENET0_GTX_CLK,
<span style="white-space:pre"> </span>ENET0_INT_N,
<span style="white-space:pre"> </span>ENET0_MDC,
<span style="white-space:pre"> </span>ENET0_MDIO,
<span style="white-space:pre"> </span>ENET0_RST_N,
<span style="white-space:pre"> </span>ENET0_RX_CLK,
<span style="white-space:pre"> </span>ENET0_RX_COL,
<span style="white-space:pre"> </span>ENET0_RX_CRS,
<span style="white-space:pre"> </span>ENET0_RX_DATA,
<span style="white-space:pre"> </span>ENET0_RX_DV,
<span style="white-space:pre"> </span>ENET0_RX_ER,
<span style="white-space:pre"> </span>ENET0_TX_CLK,
<span style="white-space:pre"> </span>ENET0_TX_DATA,
<span style="white-space:pre"> </span>ENET0_TX_EN,
<span style="white-space:pre"> </span>ENET0_TX_ER,
<span style="white-space:pre"> </span>ENET0_LINK100,
<span style="white-space:pre"> </span> Ethernet 1 //
<span style="white-space:pre"> </span>ENET1_GTX_CLK,
<span style="white-space:pre"> </span>ENET1_INT_N,
<span style="white-space:pre"> </span>ENET1_MDC,
<span style="white-space:pre"> </span>ENET1_MDIO,
<span style="white-space:pre"> </span>ENET1_RST_N,
<span style="white-space:pre"> </span>ENET1_RX_CLK,
<span style="white-space:pre"> </span>ENET1_RX_COL,
<span style="white-space:pre"> </span>ENET1_RX_CRS,
<span style="white-space:pre"> </span>ENET1_RX_DATA,
<span style="white-space:pre"> </span>ENET1_RX_DV,
<span style="white-space:pre"> </span>ENET1_RX_ER,
<span style="white-space:pre"> </span>ENET1_TX_CLK,
<span style="white-space:pre"> </span>ENET1_TX_DATA,
<span style="white-space:pre"> </span>ENET1_TX_EN,
<span style="white-space:pre"> </span>ENET1_TX_ER,
<span style="white-space:pre"> </span>ENET1_LINK100,
<span style="white-space:pre"> </span> TV Decoder //
<span style="white-space:pre"> </span>TD_CLK27,
<span style="white-space:pre"> </span>TD_DATA,
<span style="white-space:pre"> </span>TD_HS,
<span style="white-space:pre"> </span>TD_RESET_N,
<span style="white-space:pre"> </span>TD_VS,
<span style="white-space:pre"> </span>/// USB OTG controller
<span style="white-space:pre"> </span>OTG_DATA,
<span style="white-space:pre"> </span>OTG_ADDR,
<span style="white-space:pre"> </span>OTG_CS_N,
<span style="white-space:pre"> </span>OTG_WR_N,
<span style="white-space:pre"> </span>OTG_RD_N,
<span style="white-space:pre"> </span>OTG_INT,
<span style="white-space:pre"> </span>OTG_RST_N,
<span style="white-space:pre"> </span>
<span style="white-space:pre"> </span> IR Receiver //
<span style="white-space:pre"> </span>IRDA_RXD,
<span style="white-space:pre"> </span> SDRAM //
<span style="white-space:pre"> </span>DRAM_ADDR,
<span style="white-space:pre"> </span>DRAM_BA,
<span style="white-space:pre"> </span>DRAM_CAS_N,
<span style="white-space:pre"> </span>DRAM_CKE,
<span style="white-space:pre"> </span>DRAM_CLK,
<span style="white-space:pre"> </span>DRAM_CS_N,
<span style="white-space:pre"> </span>DRAM_DQ,
<span style="white-space:pre"> </span>DRAM_DQM,
<span style="white-space:pre"> </span>DRAM_RAS_N,
<span style="white-space:pre"> </span>DRAM_WE_N,
<span style="white-space:pre"> </span> SRAM //
<span style="white-space:pre"> </span>SRAM_ADDR,
<span style="white-space:pre"> </span>SRAM_CE_N,
<span style="white-space:pre"> </span>SRAM_DQ,
<span style="white-space:pre"> </span>SRAM_LB_N,
<span style="white-space:pre"> </span>SRAM_OE_N,
<span style="white-space:pre"> </span>SRAM_UB_N,
<span style="white-space:pre"> </span>SRAM_WE_N,
<span style="white-space:pre"> </span> Flash //
<span style="white-space:pre"> </span>FL_ADDR,
<span style="white-space:pre"> </span>FL_CE_N,
<span style="white-space:pre"> </span>FL_DQ,
<span style="white-space:pre"> </span>FL_OE_N,
<span style="white-space:pre"> </span>FL_RST_N,
<span style="white-space:pre"> </span>FL_RY,
<span style="white-space:pre"> </span>FL_WE_N,
<span style="white-space:pre"> </span>FL_WP_N,
<span style="white-space:pre"> </span> GPIO //
<span style="white-space:pre"> </span>GPIO,
<span style="white-space:pre"> </span> HSMC (LVDS) //
<span style="white-space:pre"> </span>HSMC_CLKIN_P1,
<span style="white-space:pre"> </span>HSMC_CLKIN_P2,
<span style="white-space:pre"> </span>HSMC_CLKIN0,
<span style="white-space:pre"> </span>HSMC_CLKOUT_P1,
<span style="white-space:pre"> </span>HSMC_CLKOUT_P2,
<span style="white-space:pre"> </span>HSMC_CLKOUT0,
<span style="white-space:pre"> </span>HSMC_D,
<span style="white-space:pre"> </span>HSMC_RX_D_P,
<span style="white-space:pre"> </span>HSMC_TX_D_P,
<span style="white-space:pre"> </span>
EXTEND IO //
EX_IO<span style="white-space:pre"> </span>
);
<span style="white-space:pre"> </span>//=======================================================
<span style="white-space:pre"> </span>// PARAMETER declarations
<span style="white-space:pre"> </span>//=======================================================
<span style="white-space:pre"> </span>//=======================================================
<span style="white-space:pre"> </span>// PORT declarations
<span style="white-space:pre"> </span>//=======================================================
<span style="white-space:pre"> </span> CLOCK //
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>CLOCK_50;
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>CLOCK2_50;
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>CLOCK3_50;
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>ENETCLK_25;
<span style="white-space:pre"> </span> Sma //
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>SMA_CLKIN;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>SMA_CLKOUT;
<span style="white-space:pre"> </span> LED //
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> [8:0]<span style="white-space:pre"> </span>LEDG;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> [17:0]<span style="white-space:pre"> </span>LEDR;
<span style="white-space:pre"> </span> KEY //
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span> [3:0]<span style="white-space:pre"> </span>KEY;
<span style="white-space:pre"> </span> SW //
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> [17:0]<span style="white-space:pre"> </span>SW;
<span style="white-space:pre"> </span> SEG7 //
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> [6:0]<span style="white-space:pre"> </span>HEX0;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> [6:0]<span style="white-space:pre"> </span>HEX1;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> [6:0]<span style="white-space:pre"> </span>HEX2;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> [6:0]<span style="white-space:pre"> </span>HEX3;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> [6:0]<span style="white-space:pre"> </span>HEX4;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> [6:0]<span style="white-space:pre"> </span>HEX5;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> [6:0]<span style="white-space:pre"> </span>HEX6;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> [6:0]<span style="white-space:pre"> </span>HEX7;
<span style="white-space:pre"> </span> LCD //
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>LCD_BLON;
<span style="white-space:pre"> </span>inout<span style="white-space:pre"> </span> [7:0]<span style="white-space:pre"> </span>LCD_DATA;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>LCD_EN;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>LCD_ON;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>LCD_RS;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>LCD_RW;
<span style="white-space:pre"> </span> RS232 //
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>UART_CTS;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>UART_RTS;
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>UART_RXD;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>UART_TXD;
<span style="white-space:pre"> </span> PS2 //
<span style="white-space:pre"> </span>inout<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>PS2_CLK;
<span style="white-space:pre"> </span>inout<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>PS2_DAT;
<span style="white-space:pre"> </span>inout<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>PS2_CLK2;
<span style="white-space:pre"> </span>inout<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>PS2_DAT2;
<span style="white-space:pre"> </span> SDCARD //
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>SD_CLK;
<span style="white-space:pre"> </span>inout<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>SD_CMD;
<span style="white-space:pre"> </span>inout<span style="white-space:pre"> </span> [3:0]<span style="white-space:pre"> </span>SD_DAT;
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>SD_WP_N;
<span style="white-space:pre"> </span> VGA //
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> [7:0]<span style="white-space:pre"> </span>VGA_B;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>VGA_BLANK_N;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>VGA_CLK;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> [7:0]<span style="white-space:pre"> </span>VGA_G;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>VGA_HS;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> [7:0]<span style="white-space:pre"> </span>VGA_R;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>VGA_SYNC_N;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>VGA_VS;
<span style="white-space:pre"> </span> Audio //
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>AUD_ADCDAT;
<span style="white-space:pre"> </span>inout<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>AUD_ADCLRCK;
<span style="white-space:pre"> </span>inout<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>AUD_BCLK;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>AUD_DACDAT;
<span style="white-space:pre"> </span>inout<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>AUD_DACLRCK;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>AUD_XCK;
<span style="white-space:pre"> </span> I2C for EEPROM //
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>EEP_I2C_SCLK;
<span style="white-space:pre"> </span>inout<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>EEP_I2C_SDAT;
<span style="white-space:pre"> </span> I2C for Audio and Tv-Decode //
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>I2C_SCLK;
<span style="white-space:pre"> </span>inout<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>I2C_SDAT;
<span style="white-space:pre"> </span> Ethernet 0 //
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>ENET0_GTX_CLK;
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>ENET0_INT_N;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>ENET0_MDC;
<span style="white-space:pre"> </span>inout<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>ENET0_MDIO;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>ENET0_RST_N;
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>ENET0_RX_CLK;
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>ENET0_RX_COL;
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>ENET0_RX_CRS;
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> [3:0]<span style="white-space:pre"> </span>ENET0_RX_DATA;
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>ENET0_RX_DV;
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>ENET0_RX_ER;
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>ENET0_TX_CLK;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> [3:0]<span style="white-space:pre"> </span>ENET0_TX_DATA;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>ENET0_TX_EN;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>ENET0_TX_ER;
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>ENET0_LINK100;
<span style="white-space:pre"> </span> Ethernet 1 //
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>ENET1_GTX_CLK;
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>ENET1_INT_N;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>ENET1_MDC;
<span style="white-space:pre"> </span>inout<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>ENET1_MDIO;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>ENET1_RST_N;
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>ENET1_RX_CLK;
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>ENET1_RX_COL;
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>ENET1_RX_CRS;
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> [3:0]<span style="white-space:pre"> </span>ENET1_RX_DATA;
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>ENET1_RX_DV;
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>ENET1_RX_ER;
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>ENET1_TX_CLK;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> [3:0]<span style="white-space:pre"> </span>ENET1_TX_DATA;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>ENET1_TX_EN;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>ENET1_TX_ER;
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>ENET1_LINK100;
<span style="white-space:pre"> </span> TV Decoder 1 //
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>TD_CLK27;
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> [7:0]<span style="white-space:pre"> </span>TD_DATA;
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>TD_HS;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>TD_RESET_N;
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>TD_VS;
<span style="white-space:pre"> </span> USB OTG controller //
<span style="white-space:pre"> </span>inout [15:0] OTG_DATA;
<span style="white-space:pre"> </span>output [1:0] OTG_ADDR;
<span style="white-space:pre"> </span>output OTG_CS_N;
<span style="white-space:pre"> </span>output OTG_WR_N;
<span style="white-space:pre"> </span>output OTG_RD_N;
<span style="white-space:pre"> </span>input OTG_INT;
<span style="white-space:pre"> </span>output OTG_RST_N;
<span style="white-space:pre"> </span> IR Receiver //
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>IRDA_RXD;
<span style="white-space:pre"> </span> SDRAM //
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> [12:0]<span style="white-space:pre"> </span>DRAM_ADDR;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> [1:0]<span style="white-space:pre"> </span>DRAM_BA;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>DRAM_CAS_N;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>DRAM_CKE;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>DRAM_CLK;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>DRAM_CS_N;
<span style="white-space:pre"> </span>inout<span style="white-space:pre"> </span> [31:0]<span style="white-space:pre"> </span>DRAM_DQ;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> [3:0]<span style="white-space:pre"> </span>DRAM_DQM;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>DRAM_RAS_N;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>DRAM_WE_N;
<span style="white-space:pre"> </span> SRAM //
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> [19:0]<span style="white-space:pre"> </span>SRAM_ADDR;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>SRAM_CE_N;
<span style="white-space:pre"> </span>inout<span style="white-space:pre"> </span> [15:0]<span style="white-space:pre"> </span>SRAM_DQ;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>SRAM_LB_N;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>SRAM_OE_N;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>SRAM_UB_N;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>SRAM_WE_N;
<span style="white-space:pre"> </span> Flash //
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> [22:0]<span style="white-space:pre"> </span>FL_ADDR;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>FL_CE_N;
<span style="white-space:pre"> </span>inout<span style="white-space:pre"> </span> [7:0]<span style="white-space:pre"> </span>FL_DQ;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>FL_OE_N;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>FL_RST_N;
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>FL_RY;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>FL_WE_N;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>FL_WP_N;
<span style="white-space:pre"> </span> GPIO //
<span style="white-space:pre"> </span>inout<span style="white-space:pre"> </span> [35:0]<span style="white-space:pre"> </span>GPIO;
<span style="white-space:pre"> </span> HSMC (LVDS) //
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>HSMC_CLKIN_P1;
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>HSMC_CLKIN_P2;
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>HSMC_CLKIN0;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>HSMC_CLKOUT_P1;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>HSMC_CLKOUT_P2;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> <span style="white-space:pre"> </span>HSMC_CLKOUT0;
<span style="white-space:pre"> </span>inout<span style="white-space:pre"> </span> [3:0]<span style="white-space:pre"> </span>HSMC_D;
<span style="white-space:pre"> </span>input<span style="white-space:pre"> </span> [16:0]<span style="white-space:pre"> </span>HSMC_RX_D_P;
<span style="white-space:pre"> </span>output<span style="white-space:pre"> </span> [16:0]<span style="white-space:pre"> </span>HSMC_TX_D_P;
<span style="white-space:pre"> </span> EXTEND IO //
<span style="white-space:pre"> </span>inout<span style="white-space:pre"> </span> [6:0]<span style="white-space:pre"> </span>EX_IO;
<span style="white-space:pre"> </span>//=======================================================
<span style="white-space:pre"> </span>// REG/WIRE declarations
<span style="white-space:pre"> </span>//=======================================================
<span style="white-space:pre"> </span>logic<span style="white-space:pre"> </span>sys_reset_n;
<span style="white-space:pre"> </span>
<span style="white-space:pre"> </span>//===== ethernet =====
<span style="white-space:pre"> </span>logic<span style="white-space:pre"> </span>enet_tx_clk_mac;
<span style="white-space:pre"> </span>logic<span style="white-space:pre"> </span>enet_tx_clk_phy;
<span style="white-space:pre"> </span>logic<span style="white-space:pre"> </span>enet_rx_clk_90deg;
<span style="white-space:pre"> </span>logic<span style="white-space:pre"> </span>enet_gtx_clk;
<span style="white-space:pre"> </span>logic<span style="white-space:pre"> </span>enet_rx_clk;
<span style="white-space:pre"> </span>logic<span style="white-space:pre"> </span>ENET0_mdio_in;
<span style="white-space:pre"> </span>logic<span style="white-space:pre"> </span>ENET0_mdio_oen;
<span style="white-space:pre"> </span>logic<span style="white-space:pre"> </span>ENET0_mdio_out;
<span style="white-space:pre"> </span>logic<span style="white-space:pre"> </span>ENET1_mdio_in;
<span style="white-space:pre"> </span>logic<span style="white-space:pre"> </span>ENET1_mdio_oen;
<span style="white-space:pre"> </span>logic<span style="white-space:pre"> </span>ENET1_mdio_out;
<span style="white-space:pre"> </span>logic<span style="white-space:pre"> </span>ena_10_from_mac;
<span style="white-space:pre"> </span>logic<span style="white-space:pre"> </span>eth_mode;
<span style="white-space:pre"> </span>logic<span style="white-space:pre"> </span>set_1k_to_mac;
<span style="white-space:pre"> </span>logic<span style="white-space:pre"> </span>set_10_to_mac;
<span style="white-space:pre"> </span>logic <span style="white-space:pre"> </span>HEX0P;
<span style="white-space:pre"> </span>logic <span style="white-space:pre"> </span>HEX1P;
<span style="white-space:pre"> </span>logic <span style="white-space:pre"> </span>HEX2P;
<span style="white-space:pre"> </span>logic <span style="white-space:pre"> </span>HEX3P;
<span style="white-space:pre"> </span>logic <span style="white-space:pre"> </span>HEX4P;
<span style="white-space:pre"> </span>logic <span style="white-space:pre"> </span>HEX5P;
<span style="white-space:pre"> </span>logic <span style="white-space:pre"> </span>HEX6P;
<span style="white-space:pre"> </span>logic <span style="white-space:pre"> </span>HEX7P;
<span style="white-space:pre"> </span>
<span style="white-space:pre"> </span>logic<span style="white-space:pre"> </span>pll_locked;
<span style="white-space:pre"> </span>logic<span style="white-space:pre"> </span>pll_phasedone;
<span style="white-space:pre"> </span>logic[7:0]<span style="white-space:pre"> </span>ssd0, ssd1, ssd2, ssd3;
<span style="white-space:pre"> </span>logic[7:0]<span style="white-space:pre"> </span>ssd4, ssd5, ssd6, ssd7;
<span style="white-space:pre"> </span>logic<span style="white-space:pre"> </span>enet_reset_n;
<span style="white-space:pre"> </span>parameter<span style="white-space:pre"> </span>ctr_width<span style="white-space:pre"> </span>=<span style="white-space:pre"> </span>20;
<span style="white-space:pre"> </span>logic[ctr_width-1:0]<span style="white-space:pre"> </span>ctr;<span style="white-space:pre"> </span>// Reset counter
<span style="white-space:pre"> </span>// ===== ethernet clock =====
<span style="white-space:pre"> </span>`ifdef NET0
<span style="white-space:pre"> </span>assign enet_rx_clk<span style="white-space:pre"> </span>= ENET0_RX_CLK;
<span style="white-space:pre"> </span>assign ENET0_GTX_CLK<span style="white-space:pre"> </span>= enet_gtx_clk;
<span style="white-space:pre"> </span>`else
<span style="white-space:pre"> </span>assign enet_rx_clk<span style="white-space:pre"> </span>= ENET1_RX_CLK;
<span style="white-space:pre"> </span>assign ENET1_GTX_CLK<span style="white-space:pre"> </span>= enet_gtx_clk;
<span style="white-space:pre"> </span>`endif
<span style="white-space:pre"> </span>// ===== MDIO Tristate
<span style="white-space:pre"> </span>assign ENET0_mdio_in<span style="white-space:pre"> </span>= ENET0_MDIO;
<span style="white-space:pre"> </span>assign ENET0_MDIO<span style="white-space:pre"> </span>= ENET0_mdio_oen ? 1'bz : ENET0_mdio_out;
<span style="white-space:pre"> </span>assign ENET1_mdio_in<span style="white-space:pre"> </span>= ENET1_MDIO;
<span style="white-space:pre"> </span>assign ENET1_MDIO<span style="white-space:pre"> </span>= ENET1_mdio_oen ? 1'bz : ENET1_mdio_out;
<span style="white-space:pre"> </span>// ===== ethernet signal =====
<span style="white-space:pre"> </span>assign ENET0_RST_N<span style="white-space:pre"> </span>= enet_reset_n;
<span style="white-space:pre"> </span>assign ENET1_RST_N<span style="white-space:pre"> </span>= enet_reset_n;
<span style="white-space:pre"> </span>// ===== ethernet control signal define
<span style="white-space:pre"> </span>assign set_1k_to_mac<span style="white-space:pre"> </span>= 1'b0;
<span style="white-space:pre"> </span>assign set_10_to_mac<span style="white-space:pre"> </span>= 1'b0;
<span style="white-space:pre"> </span>
<span style="white-space:pre"> </span>assign sys_reset_n = pll_locked;
<span style="white-space:pre"> </span>assign LEDG[8] = sys_reset_n;
<span style="white-space:pre"> </span>assign HEX0[6:0] = ssd0[6:0];
<span style="white-space:pre"> </span>assign HEX1[6:0] = ssd1[6:0];
<span style="white-space:pre"> </span>assign HEX2[6:0] = ssd2[6:0];
<span style="white-space:pre"> </span>assign HEX3[6:0] = ssd3[6:0];
<span style="white-space:pre"> </span>assign HEX4[6:0] = ssd4[6:0];
<span style="white-space:pre"> </span>assign HEX5[6:0] = ssd5[6:0];
<span style="white-space:pre"> </span>assign HEX6[6:0] = ssd6[6:0];
<span style="white-space:pre"> </span>assign HEX7[6:0] = ssd7[6:0];
<span style="white-space:pre"> </span>//=======================================================
<span style="white-space:pre"> </span>// Structural coding
<span style="white-space:pre"> </span>//=======================================================
<span style="white-space:pre"> </span>
<span style="white-space:pre"> </span>always_ff@(posedge CLOCK_50 or negedge sys_reset_n) begin
<span style="white-space:pre"> </span>if (!sys_reset_n) begin
<span style="white-space:pre"> </span>enet_reset_n<span style="white-space:pre"> </span><=<span style="white-space:pre"> </span>1'b0;
<span style="white-space:pre"> </span>ctr<span style="white-space:pre"> </span><=<span style="white-space:pre"> </span>0;
<span style="white-space:pre"> </span>end
<span style="white-space:pre"> </span>else begin
<span style="white-space:pre"> </span>if (ctr == {ctr_width{1'b1}}) begin
<span style="white-space:pre"> </span>enet_reset_n<span style="white-space:pre"> </span><=<span style="white-space:pre"> </span>1'b1;// Auto reset phy 1st time
<span style="white-space:pre"> </span>end
<span style="white-space:pre"> </span>else begin
<span style="white-space:pre"> </span>ctr<span style="white-space:pre"> </span><=<span style="white-space:pre"> </span>ctr + 1;
<span style="white-space:pre"> </span>enet_reset_n<span style="white-space:pre"> </span><=<span style="white-space:pre"> </span>1'b0;
<span style="white-space:pre"> </span>end
<span style="white-space:pre"> </span>end
<span style="white-space:pre"> </span>end
<span style="white-space:pre"> </span>enet_rx_pll pll_inst(
<span style="white-space:pre"> </span>.inclk0(enet_rx_clk),
<span style="white-space:pre"> </span>.c0(enet_rx_clk_90deg),
<span style="white-space:pre"> </span>.c1(enet_tx_clk_mac),
<span style="white-space:pre"> </span>.c2(enet_tx_clk_phy)
<span style="white-space:pre"> </span>);
<span style="white-space:pre"> </span>
<span style="white-space:pre"> </span>ddio_out ddio_out_inst(
<span style="white-space:pre"> </span>.datain_h(1'b1),
<span style="white-space:pre"> </span>.datain_l(1'b0),
<span style="white-space:pre"> </span>.outclock(enet_tx_clk_phy),
<span style="white-space:pre"> </span>.dataout(enet_gtx_clk)
<span style="white-space:pre"> </span>);
<span style="white-space:pre"> </span>
nios_core nios_inst (
<span style="white-space:pre"> </span>.clk_clk (CLOCK_50), // clk.clk
<span style="white-space:pre"> </span>.reset_reset_n (sys_reset_n), // reset.reset_n
<span style="white-space:pre"> </span>.altpll_areset_export (~KEY[0]), // altpll_areset.export
<span style="white-space:pre"> </span>.altpll_locked_export (pll_locked), // altpll_locked.export
<span style="white-space:pre"> </span>.altpll_phasedone_export (pll_phasedone),// altpll_phasedone.export
<span style="white-space:pre"> </span>.altpll_sdram_clk (DRAM_CLK), // sdram_clk.clk
<span style="white-space:pre"> </span>.altpll_vga_clk (VGA_CLK), // sdram_clk.clk
<span style="white-space:pre"> </span>.sdram_addr (DRAM_ADDR), // sdram.addr
<span style="white-space:pre"> </span>.sdram_ba (DRAM_BA), // .ba
<span style="white-space:pre"> </span>.sdram_cas_n (DRAM_CAS_N), // .cas_n
<span style="white-space:pre"> </span>.sdram_cke (DRAM_CKE), // .cke
<span style="white-space:pre"> </span>.sdram_cs_n (DRAM_CS_N), // .cs_n
<span style="white-space:pre"> </span>.sdram_dq (DRAM_DQ), // .dq
<span style="white-space:pre"> </span>.sdram_dqm (DRAM_DQM), // .dqm
<span style="white-space:pre"> </span>.sdram_ras_n (DRAM_RAS_N), // .ras_n
<span style="white-space:pre"> </span>.sdram_we_n (DRAM_WE_N), // .we_n
<span style="white-space:pre"> </span>.flash_tcm_address_out (FL_ADDR), // flash.tcm_address_out
<span style="white-space:pre"> </span>.flash_tcm_read_n_out (FL_OE_N), // .tcm_read_n_out
<span style="white-space:pre"> </span>.flash_tcm_write_n_out (FL_WE_N), // .tcm_write_n_out
<span style="white-space:pre"> </span>.flash_tcm_data_out (FL_DQ), // .tcm_data_out
<span style="white-space:pre"> </span>.flash_tcm_chipselect_n_out (FL_CE_N), // .tcm_chipselect_n_out
<span style="white-space:pre"> </span>.lcd_display_RS (LCD_RS), // lcd.RS
<span style="white-space:pre"> </span>.lcd_display_RW (LCD_RW), // .RW
<span style="white-space:pre"> </span>.lcd_display_data (LCD_DATA), // .data
<span style="white-space:pre"> </span>.lcd_display_E (LCD_EN), // .E
<span style="white-space:pre"> </span>.ledg_export (LEDG[7:0]), // ledg.export
<span style="white-space:pre"> </span>.ledr_export (LEDR), // ledr.export
<span style="white-space:pre"> </span>.sw_export (SW), // sw.export
<span style="white-space:pre"> </span>.key_export (KEY[3:1]), // key.export
<span style="white-space:pre"> </span>.ssd0_export (ssd0), // ssd0.export
<span style="white-space:pre"> </span>.ssd1_export (ssd1), // ssd1.export
<span style="white-space:pre"> </span>.ssd2_export (ssd2), // ssd2.export
<span style="white-space:pre"> </span>.ssd3_export (ssd3), // ssd3.export
<span style="white-space:pre"> </span>.ssd4_export (ssd4), // ssd4.export
<span style="white-space:pre"> </span>.ssd5_export (ssd5), // ssd5.export
<span style="white-space:pre"> </span>.ssd6_export (ssd6), // ssd6.export
<span style="white-space:pre"> </span>.ssd7_export (ssd7), // ssd7.export
<span style="white-space:pre"> </span>// the_tse_mac (RGMII)
<span style="white-space:pre"> </span>`ifdef<span style="white-space:pre"> </span>NET0
<span style="white-space:pre"> </span>.tse_pcs_tx_clock_clk (enet_tx_clk_mac), // tse_pcs_tx_clock.clk
<span style="white-space:pre"> </span>.tse_pcs_rx_clock_clk (enet_rx_clk_90deg), // tse_pcs_rx_clock.clk
<span style="white-space:pre"> </span>.tse_mac_mdio_mdc (ENET0_MDC), // tse_mac_mdio.mdc
<span style="white-space:pre"> </span>.tse_mac_mdio_mdio_in (ENET0_mdio_in),// .mdio_in
<span style="white-space:pre"> </span>.tse_mac_mdio_mdio_out (ENET0_mdio_out),// .mdio_out
<span style="white-space:pre"> </span>.tse_mac_mdio_mdio_oen (ENET0_mdio_oen),// .mdio_oen
<span style="white-space:pre"> </span>.tse_mac_rgmii_rgmii_in (ENET0_RX_DATA),// tse_mac_rgmii.rgmii_in
<span style="white-space:pre"> </span>.tse_mac_rgmii_rgmii_out (ENET0_TX_DATA),// .rgmii_out
<span style="white-space:pre"> </span>.tse_mac_rgmii_rx_control (ENET0_RX_DV), // .rx_control
<span style="white-space:pre"> </span>.tse_mac_rgmii_tx_control (ENET0_TX_EN), // .tx_control
<span style="white-space:pre"> </span>.tse_mac_status_set_10 (set_10_to_mac),// tse_mac_status.set_10
<span style="white-space:pre"> </span>.tse_mac_status_set_1000 (set_1k_to_mac),// .set_1000
<span style="white-space:pre"> </span>.tse_mac_status_eth_mode (eth_mode), // .eth_mode<span style="white-space:pre"> </span>// not use
<span style="white-space:pre"> </span>.tse_mac_status_ena_10 (ena_10_from_mac) // .ena_10<span style="white-space:pre"> </span>// not use
<span style="white-space:pre"> </span>`else
<span style="white-space:pre"> </span>.tse_pcs_tx_clock_clk (enet_tx_clk_mac), // tse_pcs_tx_clock.clk
<span style="white-space:pre"> </span>.tse_pcs_rx_clock_clk (enet_rx_clk_90deg), // tse_pcs_rx_clock.clk
<span style="white-space:pre"> </span>.tse_mac_mdio_mdc (ENET1_MDC), // tse_mac_mdio.mdc
<span style="white-space:pre"> </span>.tse_mac_mdio_mdio_in (ENET1_mdio_in),// .mdio_in
<span style="white-space:pre"> </span>.tse_mac_mdio_mdio_out (ENET1_mdio_out),// .mdio_out
<span style="white-space:pre"> </span>.tse_mac_mdio_mdio_oen (ENET1_mdio_oen),// .mdio_oen
<span style="white-space:pre"> </span>.tse_mac_rgmii_rgmii_in (ENET1_RX_DATA),// tse_mac_rgmii.rgmii_in
<span style="white-space:pre"> </span>.tse_mac_rgmii_rgmii_out (ENET1_TX_DATA),// .rgmii_out
<span style="white-space:pre"> </span>.tse_mac_rgmii_rx_control (ENET1_RX_DV), // .rx_control
<span style="white-space:pre"> </span>.tse_mac_rgmii_tx_control (ENET1_TX_EN), // .tx_control
<span style="white-space:pre"> </span>.tse_mac_status_set_10 (set_10_to_mac),// tse_mac_status.set_10<span style="white-space:pre"> </span>// not use
<span style="white-space:pre"> </span>.tse_mac_status_set_1000 (set_1k_to_mac),// .set_1000
<span style="white-space:pre"> </span>.tse_mac_status_eth_mode (eth_mode), // .eth_mode
<span style="white-space:pre"> </span>.tse_mac_status_ena_10 (ena_10_from_mac)// .ena_10<span style="white-space:pre"> </span>// not use
<span style="white-space:pre"> </span>`endif
<span style="white-space:pre"> </span>);
<span style="white-space:pre"> </span>// Flash Config
<span style="white-space:pre"> </span>assign FL_RST_N = sys_reset_n;
<span style="white-space:pre"> </span>assign FL_WP_N = 1'b1;
<span style="white-space:pre"> </span>///
<span style="white-space:pre"> </span>// LCD config
<span style="white-space:pre"> </span>assign LCD_BLON = 0; // not supported
<span style="white-space:pre"> </span>assign LCD_ON = 1'b1; // alwasy on
<span style="white-space:pre"> </span>logic <span style="white-space:pre"> </span> io_dir;
<span style="white-space:pre"> </span>logic <span style="white-space:pre"> </span> action;
<span style="white-space:pre"> </span>assign io_dir = KEY[0] & action;
<span style="white-space:pre"> </span>///
<span style="white-space:pre"> </span>// GPIO
<span style="white-space:pre"> </span>assign GPIO[17:0] = (io_dir)?GPIO[35:18]:18'hz;
<span style="white-space:pre"> </span>assign GPIO[35:18] = (io_dir)?GPIO[17:0]:18'hz;
<span style="white-space:pre"> </span>///
<span style="white-space:pre"> </span>// HSMC
<span style="white-space:pre"> </span>assign HSMC_D[1:0] = (io_dir)?HSMC_D[3:2]:2'hz;
<span style="white-space:pre"> </span>assign HSMC_D[3:2] = (io_dir)?HSMC_D[1:0]:2'hz;
<span style="white-space:pre"> </span>assign HSMC_TX_D_P = HSMC_RX_D_P;
<span style="white-space:pre"> </span>assign HSMC_CLKOUT_P1 = HSMC_CLKIN_P1;
<span style="white-space:pre"> </span>assign HSMC_CLKOUT_P2 = HSMC_CLKIN_P2;
<span style="white-space:pre"> </span>assign HSMC_CLKOUT0 = HSMC_CLKIN0;
<span style="white-space:pre"> </span>///
<span style="white-space:pre"> </span>// TV
<span style="white-space:pre"> </span>assign TD_RESET_N = TD_VS;
<span style="white-space:pre"> </span>assign action = FL_RY & TD_HS & TD_CLK27 & (TD_DATA == 8'hff);
<span style="white-space:pre"> </span>///
<span style="white-space:pre"> </span>// ps2
<span style="white-space:pre"> </span>assign PS2_CLK = PS2_DAT;
<span style="white-space:pre"> </span>assign PS2_CLK2 = PS2_DAT2;
endmodule
6. 添加qsys（也包括ddio_out、altpll）生成的qip檔案到工程中
7. assignments -> import assignments。
8. 可以編譯了
9. NIOS software builder
New application and BSP from Template
Project Template: Web Server (RGMII)
在main函數入口可以增加
#ifdef LCD_DISPLAY_NAME
lcdDevice = fopen( LCD_DISPLAY_NAME, "w" );
fprintf(lcdDevice, "Booting...\n");
fclose( lcdDevice );
#endif
便于檢視啟動狀态。
編譯。
10. 打開 nios_command_shell，注意檔案相對路徑。（用GUI操作也可以）
将ro_zipfs.zip寫入flash。注意location、base、sidp、id timestamp參數在BSP Editor中檢視，usbblaster名字也要确認。預設ro_zipfs.zip在software/yourapp/system下。
bin2flash --input="./ro_zipfs.zip" --output="./ro.flashfs_cfi_flash.flash" --location=0x100000 --verbose
nios2-flash-programmer "./ro.flashfs_cfi_flash.flash" --base 0x9000000 --sidp 0xB000140 --id 0x0 --timestamp 1353045137 --device 1 --instance 0 --cable USB-Blaster\ [2-1.5] --erase-all
然後可以下載下傳了
quartus_pgm -m jtag -c 1 -o "p;web_server.sof"
nios2-download app.elf -c USB-Blaster\ [2-1.5] -g
nios2-terminal -c USB-Blaster\ [2-1.5]
模闆生成的example中有詳細的注釋，這裡就不做代碼解釋了。