PCIe規範學習筆記

1 introduction

Link: n Tx + n Rx

Lane: 1 Tx + 1 Rx

RC

EP

Bridge

Switch

Root Complex event controller

2 configuration mechanism:

PCI compliance configuration mechanism

PCI Express enhanced configutation mechanism

Transaction layer ⇒ DLP
			four address spaces:
					memory
					IO
					configuration
					Message
	Data Link layer ⇒ DLLP
			Link Management
			Data Integrity
	Physical layer
			Logical Physical layer
			Electrical Physical layer
           

2 transaction layer

Address spaces:

memory

IO

configuration

Message

Transaction

requester ----- requests

completer ------- completions

TLP:

Transaction Layer Packets

TLP formats:

| TLP prefixes | TLP header | payload | TLP digest |

Messages:

INTx interrupt signalling(A, B, C, D)

Power Management

Error Signalling

Locked Transation

Slot Power Limit Support

Vendor-defined Messages (VDM)

LTR Messages (Latency Tolerance Reporttings)

OBFF Messages (optimized buffer flush/fill)

DRS Messages

FRS Messages

PTM Messages (precison time messurement)

VC: Virtual Channel

TC: Traffic Class

VC <===> TC mapping

Flow control:

Credit pool

Data Integrity

LCRC: Link layer CRC

ECRC: Transaction layer CRC

Ccompletion timeout

Link status

DL_Down

DL_Up

3 Data Link Layer

Data Link Control

DL_Inactive

DL_Init

DL_Active

DL_Down

DL_Up

DLLP:

Data Link Layer Packets

ACK

NAK

InitFC1, InitFC2, UpdataFC

4 Phsical Layer

Logical physical

Electrical physical

2.5GT/s ===> 8b/10b encoding

8GT/s ===> 128/130b encoding

LTSSM:

Detect

Polling

Configuration

Recovery

L0

L0s

L1

L2

Disable

Loopback

Hot Reset

5 Power Management

L0

L0s

L1

L1.1

L1.2

L2

L3

PME:

Power Management Event

ASPM:

Active State Power Management

Device power management states:

D0, D1, D2, D3

6 System Architecture

todo…

7 System

這一章是最重要的。

todo…