imut_du FPGA_作業2

當我對着這個圖，根據中間狀态A、B、C，E，因為我是嚴格按照這個圖來程式設計式，為了達到這個圖的效果，然後分析，然後列出了表達式和真值表和表達式，

列完寫代碼

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY w_s IS
PORT (
A_1,A_2,B_1,B_2,D_1: IN STD_LOGIC;
E_OUT: OUT STD_LOGIC
);
END w_s;

ARCHITECTURE ART OF w_s IS
SIGNAL SEL: STD_LOGIC_VECTOR(4 DOWNTO 0); 
BEGIN 
SEL <=A_1&A_2&B_1&B_2&D_1;
WITH SEL SELECT
E_OUT <= A_1 AND A_2 WHEN ("11000" OR"11001"),
         B_1 OR B_2 WHEN ("00101" OR"00100"OR"00011"OR"00111"),
         B_2 AND (NOT D_1) WHEN "00010",
         '0'  WHEN ("00000" OR"00001"),
        ((A_1 AND A_2) OR(B_1 OR B_2)OR ( (NOT D_1) AND B_2)) WHEN OTHERS;
      
END ART;      

編譯成功後

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