Different capacitance values and quantities of capacitors are designed in the schematic diagram, and the influence of the decoupling radius is also considered, so how should these capacitors be placed in the PCB layout?
According to the relevant literature, the factors affecting the decoupling radius of the decoupling capacitor include frequency, power supply ground plane impedance, power supply ground plane thickness, dielectric constant of the power supply ground plane, capacitance value and equivalent series inductance, among which the power supply ground plane impedance has the most significant influence on the decoupling radius of the decoupling capacitor. The stackup design and via placement in the PCB have different effects on the ground plane impedance of the power supply, introducing a series of different parasitic parameters, resulting in impedance changes, resonant frequency shifts, and so on.
The resonant frequency generation conditions are calculated in the discussion of the capacitor decoupling radius, and the placement of capacitors, traces, and vias in practical engineering will affect the resonant frequency. PCB layout trace capacitors typically pull traces at the pad through one or more vias to the power ground plane, and in high-speed signals, both traces and vias will have parasitic inductance and other parameters.
The parasitic inductance generated by capacitance to point of load, vias, and pads is most affected by the parasitic inductance of vias, which can be estimated by formulas:
where L is the parasitic inductance, united in nH; h is the length of the via, in inch; d is the diameter of the via, unit: inch; 1inch=1000mil=2.54cm=25.4mm。 According to the formula, the longer the via length, the greater the parasitic inductance. The larger the diameter, the smaller the parasitic inductance.
Capacitor traces come out with at least two vias with the equivalent parasitic inductance in series, and parallel vias can be added to reduce the equivalent parasitic inductance, but this depends on the layout and production process. The total inductance of an inductor series increases as follows:
If other conditions remain constant, the inductance L increases, and the self-resonant frequency of the capacitor soldered on the PCB decreases, the decoupling effect on the high frequency band will be weakened. Based on the above analysis, measures are taken to reduce the parasitic inductance in the PCB layout traces, and the direction of the capacitor layout traces is optimized, and a short section of traces from the pads is often taken through different vias to enter the power plane and the ground plane.
As shown in the figure below, when decoupling the IC pins, shorten the trace length between the pad and the decoupling capacitor as much as possible, too long the trace will introduce additional parasitic inductance, so that the total inductance of the decoupling capacitor increases, as calculated by the above formula, the increase of additional parasitic inductance will make the resonant frequency decrease, affect the decoupling characteristics of the capacitor, and make the frequency range of effective noise filtering deviate from the resonant frequency point.
The decoupling capacitor shares a hole or power port with the IC pins, which is beneficial for improving the decoupling effect without increasing the length of the traces, as shown in the figure below.
It is common for ICs to use more decoupling capacitors in parallel, and for BGA ICs, planar decoupling is generally used, and the goal is to take measures to shorten the trace length as much as possible. In planar decoupling, the IC power supply pin and the ground pin are not directly adjacent to each other, and the position and vias of the decoupling capacitor are placed next to the IC power supply pin, and the power supply and ground pin are connected through the power plane and the ground plane and the two ends of the decoupling capacitor.
BGA IC has a large number of power pins and ground pins, and many times it is not possible to meet the needs of a decoupling capacitor on each pin, so one or several decoupling capacitors are generally arranged in a region to decouple several power pins at the same time. Combined with the discussion of decoupling capacitors in the previous tweet, in the layout of decoupling capacitors, the capacitors with small capacitance values are close to the IC pins, and the large capacitance values can be slightly farther away from the IC, and the decoupling capacitors of each specification are evenly and symmetrically arranged around the IC, which can evenly decouple the power supply in the area where the IC is located, and can also cancel out the magnetic flux generated by the internal current, thereby reducing the influence of the lead inductance of the decoupling capacitor.
As shown in the figure above, for a multilayer board with a small distance between the power plane and the ground plane, it is important to consider whether excessive inductance will be introduced by considering the path of the connection between the decoupling capacitor and the IC pins, the number of vias, and the number of layers passed. If the IC placement layer is closer to the ground layer, the decoupling capacitor should be placed closer to the power supply pin; If the IC placement layer is closer to the power plane, the decoupling capacitor should be placed closer to the ground pin.
In summary, the idea of placing vias is to reduce the current loop area as much as possible, thereby reducing the parasitic inductance. As shown in the figure, there are several common ways to place capacitors via holes.
Summary of the above wiring methods:
1. The occurrence of pad trace connection vias is too long, resulting in the introduction of excessive parasitic inductance;
2. Punching holes at the end of the pad, the area of the current loop is significantly reduced, and the parasitic inductance of the trace is reduced.
3. Further reduce the area of the current loop, and the vias are punched on the side of the pad;
4. Parallel vias, and the pads are copper poured to further reduce the parasitic inductance;
5. Directly punch holes on the pad to minimize the parasitic inductance, but this method will be affected by the manufacturing and production methods, and the use needs to be comprehensively evaluated.