As with all non-ideal electrical components, the inductors provided in the component kit are not perfect. Figure 1 shows a simplified circuit diagram of a common actual inductor. In addition to the required inductance L, the actual component will have a loss (modeled as a series resistor, denoted by R in the diagram) and a parallel parasitic capacitance (denoted by C). The smaller the resistance (close to 0 Ω) and the smaller the capacitance (close to 0 F), the better the inductance.
Figure 1.3 Element LRC inductance model.
Inter-winding capacitance and self-resonant frequency
C usually denotes the turn-to-turn distributed capacitance of the inductor (and the capacitance between turns and core, etc.). At a specific frequency (SRF), this inter-turn capacitance will form a parallel resonance with the inductor L, turning the inductor into a tuned circuit.
3-element LRC model impedance and frequency
At frequencies below SRF, the model is inductive. At frequencies above SRF, the model is capacitive, and at SRF frequencies, the model is resistive because the magnitude of the inductive and capacitive reactances is equal and the phases are opposite, thus canceling each other.
Under the SRF of the inductor, all of the following conditions are met:
- The input impedance is at its peak.
- The phase angle of the input impedance is zero, changing from positive (inductive) to negative (capacitive).
- Since the phase angle is zero, Q is also zero.
- The effective inductance is zero because the negative capacitive reactance (XC = 1/jωC) just cancels out the positive reactance (XL = jωL).
- The 2-port insertion loss (S21 dB) reaches a maximum, corresponding to the minimum value in the frequency vs. S21 dB graph.
- The 2-port phase (S21 angle) is zero, changing from a negative value at a lower frequency to a positive value at a higher frequency.
Equation 1 represents the SRF vs. inductance and capacitance in the inductance model circuit.
Thereinto:
L is the inductance in H
Cp is the parasitic capacitance in F
Equation 1 makes it clear that increasing the inductance or capacitance will lower the measured SRF value, while decreasing the inductance or capacitance will increase the SRF value.
Pre-lab simulation of a 3-element LRC inductance model
Figure 2 shows a simulated test circuit for a 3-element LRC inductance model. L, R, and CP are used to model inductance. V1 is the ideal AC test voltage source, and the resistance RS indicates the source resistance of V1. CL and RL are load elements where CL is set to the typical input capacitance of the oscilloscope input channel ADALM2000. The RL can be set to RS or to a higher value, such as a 1 MΩ input resistance for an oscilloscope channel.
Figure 2: Simulation schematic.
Before actually building an inductance test circuit, you should simulate it using the circuit shown in Figure 2.
As shown in Figure 3, for the example of a 1 mH inductor L, we performed two frequency sweep simulations with a frequency range of 10 kHz to 10 MHz, where CP was set to 15 pF and R was set to 100 mΩ. The red curve indicates that the RL is set to the same 200 Ω as the RS. When the inductor impedance reaches its maximum, the amplitude measured at RL drops dramatically at SRF. The blue curve indicates that the RL is set to 1 MΩ at the oscilloscope input. Similarly, when the impedance reaches its maximum, we observe a sharp drop in the zero point. We also see a noticeable spike in the amplitude of the RL, about an octave below the notch. This spike occurs when the source resistance and load resistance do not match.
Figure 3: Simulation results: red curve RL = 200 Ω, blue curve RL = 1 MΩ.
material
- ADALM2000 active learning modules
- Solderless breadboards and jumper kits
- A 1 mH inductor
- Other inductances of different values
- Two 200 Ω resistors (can be made up of two 100 Ω resistors in series)
illustrate
An inductance test circuit as shown in Figure 4 is constructed on a solderless breadboard. The blue squares indicate the locations where the ADALM2000 AWG and the oscilloscope channels are connected.
Figure 4: Inductance test circuit.
Hardware settings
The connection of the ADALM2000 AWG output and the oscilloscope channel input is shown in the blue box in Figure 4. The component kit should contain several inductors with different values. Insert the inductors into the test circuit one by one.
Procedure Steps
Open the Network Analyzer software tool in the Scopy window. Configure the scan range with a start frequency of 100 kHz and a stop frequency of 30 MHz. Set the amplitude to 1 V, the offset to 0 V, and the amplitude range of the Bord plot to –60 dB to +40 dB. Set the maximum phase to +180° and the minimum phase to –180. In the channel options, click on channel 1 to make it a reference channel. Set the number of steps to 100.
Run a single scan for each inductor in the part kit. You should see that the amplitude and phase vs. frequency curves are very similar to the simulation results. Export data to a .csv file for in-depth analysis using Excel or MATLAB®.
Figure 5: Inductance test circuit breadboard connection
图6. Scopy截图，L = 100 μH，RL = 200 Ω。
图7. Scopy截图，L = 100 μH，RL = 1 MΩ。
Issue:
The SRF formula is used to calculate the inter-turn parasitic capacitance of the inductor used in the experimental setup.
You can find answers to your questions on the Student Area forum.
Additional experiments
To further explore this resonant phenomenon, connect the external 39 pF and/or 100 pF capacitors in parallel with the inductor and remeasure the frequency response. This allows for more resonant frequency data, and the resonance formula can also be used to calculate and confirm the inductances L and CP in the simplified model.