Intel's first CPU, 4004, released in 1971, had about 2,300 internal transistors, and five years later, Intel's Ponte Vecchio processor packaged more than 100 billion transistors with 47 small chips into a single processor, using both 2.5D and 3D technology in the process.
On January 5, 2022, AMD released the first 3D stacked desktop processor Ryzen 7 5800X3D, which benefits from 3D chip stacking, compared to Zen2, Zen 3 average performance is 19%.
On March 4, 2022, AI chip company Graphcore's Bow IPU chip used 3D stacking technology to increase AI speed by 40%.
On March 9, 2022, Apple released the M1 Ultra, the computer's highest-end processor chip, which connects 2 chips arranged horizontally to each other, equipped with 114 billion transistors.
Various examples show that 2.5D/3D packaging technology is becoming an important means of improving chip performance. The importance of 3D stacking technology is increasing by achieving the highest levels of silicon integration and area efficiency at the lowest cost. New applications are also emerging, and 3D stacking technology has become a lucrative solution to meet the performance required by applications such as artificial intelligence, machine learning, and data centers.
3D packaging is the trend of the times, and the technical challenges should not be underestimated
As chip shrinkage becomes more and more difficult, and the market chases the high performance of chips, the industry has begun to explore the field of packaging to seek breakthroughs, so in recent years, advanced IC packaging technology such as 2.5D/3D has become a part of the foundry, packaging and testing plant, IDM, chip designers and EDA manufacturers are competing for attention.
However, due to cost reasons, advanced packaging is mainly used for high-end, niche-oriented applications such as HPC. 3D packaging technology has ushered in rapid development driven by major industries such as HPC. According to the Advanced Packaging Market Analysis Report released by Yole 2022Q1, the overall revenue of the advanced packaging market is expected to grow at a compound annual growth rate of 10.11%, from $32.1 billion in 2021 to $57.2 billion in 2027. Among the various sub-categories of packaging, the 2.5D/3D packaging market has the largest compound annual growth rate, from $6.7 billion in 2021 to $14.7 billion in 2027, up to 14.34%.
Advanced Packaging Market Revenue and Forecast
(Source: Yole)
Not just the final step in the chip manufacturing process, packaging is becoming a catalyst for chip innovation. 3D packaging technology allows different chips such as CPUs, accelerators, memory, IO, power management, etc. to be pieced together like LEGO bricks, and its main advantage is that it can achieve better interconnection energy efficiency and reduce access latency. For example, 3D packaging technology allows more memory to be placed near the computing core, so it can reduce the total wiring length, increase memory access bandwidth, improve latency, increase CPU performance, and thus greatly improve product-level performance, power consumption, and area, while enabling a comprehensive and rethinking of the system architecture.
Today, 3D packaging has become one of the key technologies for the industry's top chip companies such as Intel, AMD, NVIDIA, Apple and so on. Although heterogeneous packaging represented by 3D ICs has become a key development direction in the future, the implementation of new technologies will face many thorny problems. Compared with traditional packaging technology, 2.5D/3D IC heterogeneous packaging is not only an innovation in the technology of the packaging factory, but also brings challenges to the original design process, design tools, simulation tools, etc.
First of all, after the 2.5D/3D stacking, due to the great increase in the degree of integration, the heat generation becomes more concentrated, and heat dissipation is a major problem; Secondly, in the process of chip, intermediary layer, substrate expansion and cold contraction, it is necessary to ensure the reliability of mechanical stress; In addition, the high-frequency signals between chips need to meet the timing and signal integrity requirements. Finally, after the chip stacking is completed, it is also necessary to test whether the upper layer chip can work properly, whether the wiring is good, and it is not damaged during the stacking process. These are the challenges and challenges that 3D packaging needs to face.
3D packaging is a major undertaking for the whole industry chain to cooperate together
Therefore, in this context, 3D packaging requires the support of multiple links in the supply chain, including foundries, packaging plants, EDA manufacturers, material manufacturers and so on.
When it comes to 3D packaging, foundries like TSMC, Samsung, and Intel are the mainstay. TSMC's "3D Fabric", Intel's "Foveros" and Samsung's "X-cube" are the three representative brands of 3D packaging technology. According to market research firm Yole Development, intel and TSMC accounted for 32% and 27% of global investment in advanced packaging in 2022 in 2022, respectively, and Samsung Electronics ranked fourth (the third is Sun Moonlight).
2.5D and 3D packaging solutions at a glance
(Source: Yole)
Those familiar with TSMC know that TSMC has integrated its 2.5D and 3D advanced packaging and chip stack technologies such as SoIC (System Integration Chip), InFO (Integrated Fan-Out Packaging Technology), CoWoS (Chip on-Chip On-Board Packaging) into the "3D Fabric" brand. According to TSMC's 2022Q2 earnings briefing, most of the 3DIC and SoIC technologies developed by TSMC for HPC applications have begun to be adopted by customers, and TSMC has also established a 3DIC center in Japan and held an opening ceremony in June this year.
Image source: SemiWiKi
Intel has used The Coveros 3D packaging technology for its Ponte Vecchio and Rialto Bridge GPUs and Agilex FPGAs, and Intel says chips produced in 3D Foveros packages are in some cases extremely competitive compared to standard monolithic (single-chip) chip designs. Intel announced in May 2021 that it would spend $3.5 billion on the New Mexico Coveros fab.
Image source: Intel
Samsung's core competencies in 3D packaging come from TSV and PoP technologies. In June 2022, Samsung established the Semiconductor Packaging Working Group, showing Samsung's emphasis on advanced packaging, including 3D packaging.
In addition to foundries, traditional packaging manufacturers are also actively transitioning to 3D packaging technology. Sealing the test faucet Sun Moonlight is a more powerful member. In June 2022, Sun Moonlight launched the VIPack 3D advanced packaging platform, which is composed of six core packaging technologies, including Fan Out Package-on-Package (FOPoP), Fan Out Chip-on-Substrate (FOCoS), Fan Out Chip-on-Substrate-Bridge (FOCoS-Bridge) based on high-density RDL and Fan Out System-in-Package (FOSiP), as well as 2.5D/3D ICs and Co-Packaged Optics based on silicon through-hole (TSV). Other packaging and testing plants such as Anku, Changdian Technology, Tongfu Microelectric, etc. are also accumulating power in the field of 3D packaging.
In addition, to manufacture 3D chips, new technological innovations in the field of manufacturing equipment and raw materials are needed. One of the key important materials is the ABF carrier board for the connection of multiple chips. ABF carrier board is one of the IC carrier board, ABF carrier board can be made of thin lines, suitable for high pin number high message transmission IC, with high computing performance, mainly used for CPU, GPU, FPGA, ASIC and other high computing performance chips. In recent years, the development of technologies such as Chiplet has increased the demand for ABF carrier boards, and there are also issues such as how to improve connection speed, improve heat dissipation, and reduce costs. At present, major ABF carrier board suppliers including Xinxing, Jingshuo, Nandian, Ibiden, Shinko, AT&S and other major ABF carrier board suppliers have carried out certain expansions.
Ic carrier board is a product between IC semiconductors and PCBs, as a bridge between the chip and the circuit board, can protect the integrity of the circuit, while establishing an effective heat dissipation path.
Image source: stockfeel
However, the challenges faced by 3D IC packaging can sometimes not be solved by the manufacturing side alone, and need to be planned in advance at the beginning of the chip design. 3D IC packaging will not only be a matter of "packaging", but also more reflected in the synergy of chips and packages.
The most fundamental challenge with 3D IC packaging comes from the transformation of application tools databases. The chip-specific GDS format is fundamentally different from the Gerber format used by PCBs and requires a re-integration of solutions to meet advanced packaging requirements. In addition, the complexity of scale growth is also an issue that needs to be focused on. When doing multi-die, in the face of increasingly large systems, it is necessary to consider whether it can be undertaken and verified. Another noteworthy thing is the design planning, how to connect multiple chips, which tools to use to plan, which document is the official "golden reference" version, all need to be established in advance. Only when a plan is established can subsequent design and verification be carried out. This is where the importance of the EDA tool is highlighted.
And that's where EDA vendors like Siemens EDA come in, which has a proven end-to-end EDA solution that combines its Xpedition, HyperLynx and Calibre technologies to enable fast and efficient design-to-GDS sign-off. For example, in the chip simulation verification phase, combined with the Siemens HyperLynx and Calibre series of tools, it is possible to handle the synergy problems of die, package and PCB simulation, rather than focusing on a single design area; In the chip package design layout stage, Siemens Xpedition Package Designer provides high-performance advanced packaging technology support, as well as intelligent layout functions, which can improve the efficiency of package design layout and shorten layout time; During the test phase, the Siemens EDA Tessent tool platform is based on industrial analysis and provides an integrated and smooth EDA solution for 3D ICs, achieving the goal of increasing test coverage, reducing test costs, and tracking yield issues through a flexible and complete test portfolio.
At the same time, collaboration between EDA vendors and foundries and package plants is becoming increasingly important. In this regard, Siemens EDA has actively cooperated with TSMC, Samsung and Sun Moonlight to provide them with ecological support.
Among them, as early as 2020, Siemens EDA won TSMC's "Joint Development of 3DIC Design Productivity Solution" OIP Partner of the Year Award, and in 2021, the two sides reached key milestones in cloud IC design and TSMC's 3D silicon stacking and advanced packaging technology series - 3DFabric™. In addition, Siemens EDA's high-density advanced packaging solutions have been certified by Samsung Foundationry's latest packaging process. Siemens EDA also leveraged its Xpedition™ Substrate Integrator software and calibre® 3DSTACK platform to support the next generation of high-density advanced package designs with Riyueguang, according to Dr. Zhibin Hong, Vice President of Riyueguang Group, "The cooperation between the two parties allows customers to reduce the package planning and verification cycle of 2.5D/3D ICs and FOCoS, which can be reduced by approximately 30% to 50% in each design cycle. Design development time. ”
epilogue
As the entire industry chain gradually improves, and continues to introduce new supported technologies in various fields, such as 2.5D and 3D packaging technology will become the mainstay of the next chip performance improvement process, and will also be the future of the semiconductor industry. 3D packaging is changing the world of semiconductors, and this time it will cause changes in the entire industry chain.