Renesas Electronics of Japan has released the world's first PCI-E 6.0 standard timing scheme, including 11 clock buffers, 4 multiplexers, and clock generators, providing a complete product line for data centers, cloud computing, networking, and high-speed industrial applications.
Renesas' PCI-E 6.0 clock buffers are available with 4, 8, 13, 16, 20, and 24 outputs, and multiplexers are available with 2, 4, 8, and 16 outputs, all in package sizes of just 3×3mm.
Renesas said that while the PCI-E 6.0 bandwidth increases, clock jitter does not exceed 100fps RMS, while Renesas' RC190xx series clock buffers and RC192xx series multiplexer clock jitter is only 4fps RMS, which is equivalent to almost no noise.
At the same time, the input and output delay is 1.4ns, the output output deviation is 35ps, and the power supply voltage rejection ratio (PSRR) -80dB@100kHz can ensure sufficient system stability, and support power failure tolerance (PDT) and elastic start sequence (FSS) to ensure the stability of a system state.
In addition, the power consumption is also reduced by 30% compared to the previous generation.
Previous information shows that the new PCI-E 6.0 specification can achieve a single channel to reach a transmission rate of 8GB/s, which is equivalent to the full rate of PCI-E 2.0 x16, while PCI-E 6.0 x16 will achieve an exaggerated one-way 128GB/s and a bidirectional 256GB/s.
Looking back at the PCI-E 6.0 version process, in fact, in the summer of 2019, it has begun to discuss, as a follow-up product of PCI-E 5.0, PCI-SIG plans to use 3 years to iterate on its version, that is, when the PCI-E 5.0 standard is completed in 2019, the PCI-E 6.0 specification has begun to be formulated, looking for the possibility of improving PCI-E bandwidth. Although the PCI-SIG missed its goal of completing the PCI-E 6.0 specification by the end of 2021, it still appears that the efficiency is still staggering.