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In addition to advanced processes, advanced packaging has also become a key technology to continue Moore's Law, and technologies such as 2.5D, 3D and Chiplets have become hot topics in the semiconductor industry in recent years. Exactly, how do advanced encapsulation play a key role in perpetuating Moore's Law? And what are the characteristics of packaging technologies such as 2.5D, 3D and Chiplets?
Artificial intelligence (AI), Internet of Vehicles, 5G and other applications have emerged, and all must use high-speed computing, high-speed transmission, low latency, low energy consumption of advanced functional chips; however, with the growth of computing demand in multiples, how to continue Moore's Law has become a major challenge in the semiconductor industry.
Chip scaling became more difficult, and heterogeneous integration was born
In other words, advanced semiconductor processes have entered 7 nanometers, 5 nanometers, and then began to move towards 3 nanometers and 2 nanometers, so the size of the transistor is constantly approaching the physical volume limit of atoms, and the limitations of electrons and physics have also made it more and more difficult for advanced processes to continue to shrink and upgrade.
Therefore, in addition to the continuous development of advanced processes, the semiconductor industry has also begun to find other ways to maintain a small size of the chip while maintaining high efficiency; and the layout design of the chip has become a new solution to the continuation of Moore's Law, and the concept of heterogeneous integration Design Architecture System (HIDAS) has come into being, and has become the innovative kinetic energy of IC chips.
The so-called heterogeneous integration, in a broad sense, is to integrate two different chips, such as memory + logic chips, optoelectronics + electronic components, etc., through packaging, 3D stacking and other technologies. In other words, the integration of two different processes and chips of different properties can be called heterogeneous integration.
Because the application market is more diverse, the cost, performance and target group of each product are different, so the heterogeneous integration technology required is not the same, and the trend of market differentiation is gradually emerging. To this end, IC foundry, manufacturing and semiconductor equipment industry have invested in heterogeneous integration development, 2.5D, 3D packaging, Chiplets and other popular packaging technologies, is based on the idea of heterogeneous integration, mushrooming.
The 2.5D package effectively reduces chip production costs
In the past, to integrate chips together, most of them used System in a Package (SiP) technology, such as PiP (Package in Package) packaging, PoP (Package on Package) packaging, etc. However, with the application of smart phones, AIoT and other applications, not only need higher performance, but also to maintain a small size, low power consumption, in such a case, we must find a way to stack up more chips to make the volume shrink, therefore, the current packaging technology in addition to the original SiP, have also been towards the development of stereoscopic packaging technology.
In general, stereoscopic packaging means that the "silicon interposer" made of silicon wafers is directly used, and instead of using the "wire carrier board" made of plastic in the past, several chips with different functions are directly packaged into a chip with higher performance. In other words, it is to continuously superimpose silicon chips on top of silicon in a way that stacks high chips, improving process costs and physical limitations, so that Moore's Law can continue to be realized.
The stereoscopic package is more well known as the 2.5D and 3D packages, which start with the 2.5D package. The so-called 2.5D package, the main concept is the processor, memory or other chips, side by side on the silicon interposer (Silicon Interposer), first through the micro bump (Micro Bump) connection, so that the silicon intermediation board within the metal wire can be connected to the electronic signal of different chips; and then through the silicon perforation (TSV) to connect the metal bump below (Solder Bump), and then through the wire carrier board to connect the external metal ball, to achieve the chip, Tighter interconnect between the chip and the package substrate.
2.5D and 3D packages are popular stereoscopic packaging technologies. （Source：ANSYS）
The well-known 2.5D packaging technology is nothing more than TSMC's CoWoS. The CoWoS technology concept, in simple terms, semiconductor chips (such as processors, memories, etc.) are placed on a silicon interposer layer, and then connected to the underlying substrate through the chip on Wafer (CoW) packaging process. In other words, the chip is first connected to the silicon wafer through the chip on Wafer (CoW) packaging process, and then the CoW chip is connected to the substrate and integrated into CoWoS; using this packaging mode, multiple chips can be packaged together, through the Si Interposer interconnection, to achieve the effect of small package size, low power consumption, and few pins.
TSMC CoWos packaging technology concept. (Source: TSMC)
In addition to CoWos, fan-out wafer-level packaging can also be classified as a way of being a 2.5D package. The principle of fan-out wafer-level packaging technology is to pull out the required circuit from the end of the semiconductor bare crystal to the Redistribution Layer to form the package. Therefore, there is no need to package the carrier board, no wire (Wire), bump (Bump), which can reduce the production cost by 30% and make the chip thinner. At the same time, it also reduces the chip area a lot, and can also replace the higher cost of straight-through silicon crystal perforation, to achieve the goal of integrating different component functions through packaging technology.
Of course, stereoscopic packaging technology is not only 2.5D, but also 3D packaging. So, what is the difference between the two, and 3D packaging is being adopted by semiconductor industry?
Compared to 2.5D packaging, the principle of 3D packaging is to make a transistor (CMOS) structure on a chip, and directly use silicon perforation to connect the electronic signals of different chips on top of and below to directly stack memory or other chips vertically on top of it. The biggest technical challenge of this package is that it is extremely difficult to make silicon piercing directly in the chip, but due to the rise of high-performance computing, artificial intelligence and other applications, coupled with the increasing maturity of TSV technology, we can see more and more CPUs, GPUs and memory begin to use 3D packaging.
3D packaging is a direct stacking of chips. (Source: Intel)
TSMC and Intel are actively developing 3D packaging technology
In the 3D package, Intel and TSMC have their own technologies. Intel uses "Foveros" 3D packaging technology, using heterogeneous stacking logic processing operations, which can stack the various logic chips together. That is to say, for the first time, chip stacking has been extended from traditional passive silicon intermediaries and stacked memory to high-performance logic products such as CPUs, graphics and AI processors. In the past, stacking was only used for memory, and now heterogeneous stacking is used only for memory, and now heterogeneous stacking is used, so that memory and computing chips can be stacked in different combinations.
In addition, Intel has developed three new technologies, namely Co-EMIB, ODI and MDIO. Co-EMIB can connect higher computing performance and power, and can interconnect two or more Coveros components, as well as designers can connect simulators, memories, and other modules at very high bandwidths and very low power consumption. ODI technology provides greater flexibility for all-round interconnect communication between small and medium-sized chips in the package. The top chip can communicate with other small chips like EMIB technology, and can also communicate vertically with the bottom die below via a silicon through a silicon through hole (TSV) like Coveros technology.
Intel Coveros technology concepts. (Source: Intel)
At the same time, the technology also utilizes large vertical through-holes to supply power directly from the package substrate to the top die, which is much larger than traditional silicon through-holes, with lower resistance, thus providing more stable power transmission, and enabling higher frequency width and lower latency through stacking. This approach reduces the number of through-silicon vias required in the substrate chip, frees up more area for the active components, and optimizes die size.
TSMC, on the other hand, proposed an integrated solution for "3D multi-chip and system integration chip" (SoIC). This system-integrated chip solution stacks different sizes, process technologies, and known-good bare crystals of materials directly on top of each other.
TSMC mentioned that compared with the traditional 3D integrated circuit solution using micro-bumps, the bump density and speed of the integrated chip in this system are several times higher, while greatly reducing power consumption. In addition, SSCs are front-end process integration solutions that connect two or more bare dies prior to packaging; as a result, SSP chipsets can leverage the company's Back-end Advanced Packaging Technologies from InFO or CoWoS to further integrate other chips to create a robust "3D×3D" system-level solution.
In addition, TSMC has also launched 3DFabric, which integrates the fast-growing 3DIC system integration solution to provide greater flexibility and create a powerful system through solid chip interconnects. With different options for front-end chip stacking and rear-end packaging, 3DFabric assists customers in connecting multiple logic chips together, even in series high-bandwidth memory (HBM) or heterogeneous chiplets such as analog, input/output, and RF modules. 3DFabric combines solutions for rear and front 3D technologies and complements the crystal microfiber, continuously improving system performance and functionality, reducing size and appearance, and accelerating time-to-market.
After introducing 2.5D and 3D, Chiplets is also one of the most popular advanced packaging technologies in the semiconductor industry, and finally, let's briefly explain the characteristics and benefits of Chiplets.
In addition to 2.5D and 3D packages, Chiplets is also one of the most talked about technologies. Due to the development of electronic terminal products towards a high integration trend, the demand for high-performance chips continues to increase, but with Moore's Law gradually slowing down, in the process of continuously improving product performance, if the chip area is increased in order to integrate new functional chip modules, it will face cost increases and low yield problems. As a result, Chiplets has become a technological alternative to the semiconductor industry's bottleneck due to Moore's Law.
Chiplets are like puzzles, turning small chips into big chips
The concept of Chiplets originated from the multi-chip module born in the 1970s, and its principle is roughly speaking, that is, it is composed of multiple homogeneous, heterogeneous and other smaller chips to form a large chip, that is, from the original chip designed in the same SoC, it is split into many different small chips and manufactured separately and then packaged or assembled, so the chip that is called the spin-off chip Chiplets.
Due to the rapid rise in the cost of advanced processes, unlike the SoC design method, the large size of the multi-core design, dispersed to smaller chips, can better meet the needs of today's high-performance computing processors, and the flexible design method not only improves flexibility, but also has better yield and cost saving advantages, and reduces the chip design time schedule, accelerating chip Time to market time.
There are three main benefits to using Chiplets. Because the cost of advanced processes is very high, especially analog circuits, I/O, etc. are becoming more and more difficult to shrink with process technology, and Chiplets is to divide the circuit into independent small chips, and strengthen the functions, process technology and size of each, and finally integrate together to overcome the challenge of difficult to shrink the process. In addition, Chiplets can also use existing mature chips to reduce development and verification costs.
Many semiconductor companies have adopted Chiplets to introduce high-performance products. Intel's Intel Stratix 10 GX 10M FPGAs, for example, are designed with Chiplets to achieve higher component density and capacity. Based on the existing Intel Stratix 10 FPGA architecture and Intel's advanced embedded multichip Interconnect Bridging (EMIB) technology, the product uses EMIIB technology to combine two high-density Intel Stratix 10 GX FPGA core logic chips with corresponding I/O units. The same goes for AMD's second-generation EPYC family of processors. Unlike the first generation of Chiplets, which combined Memory and I/O into a 14nm CPU, the second generation combined I/O and Memory into a chip and cut the 7nm CPU into 8 Chiplets for combination.
All in all, the past chip performance has relied on the improvement of the semiconductor process and improved, but as the component size is getting closer and closer to the physical limit, the chip shrinkage difficulty is getting higher and higher, to maintain a small size, high-efficiency chip design, the semiconductor industry not only continues to develop advanced processes, but also towards the chip architecture to improve, so that the chip from the original single layer, to multi-layer stacking. Because of this, advanced packaging has also become one of the key drivers of improving Moore's Law, leading the way in the semiconductor industry.