When it comes to semiconductor equipment, lithography machines are often mentioned. But in fact, there are some very important devices in the semiconductor field, such as ATE (Automatic Test Equipment) is one of the important categories.
According to Wikipedia, the so-called ATE refers to the equipment that can use automation technology to quickly test products. Specific to the semiconductor field, it refers to the equipment used for CP (Chip Probe) and FT (Final Test) testing in the chip manufacturing process. Only after these two steps can the reliability of the chip delivered to the developer be guaranteed as much as possible.
With the steady advancement of the chip (especially SoC) process, the manufacturing cost continues to increase, as an important part of the chip production process, the importance of testing is getting higher and higher, which brings great challenges to the corresponding ATE suppliers. Recently, Huang Feihong, deputy general manager of sales of Teradyne, the world's leading ATE supplier, shared the evolution of the market's demand for ATE and their countermeasures.
Gradient SoC testing requirements
Huang Feihong said that in the decades from 1990 to 2025, the process has evolved rapidly. At the same time, there is also a greater demand for ATE.
According to reports, the 90s was the era of vigorous development of CMOS, when the functions of semiconductor SoC chips were getting stronger and stronger, and the ability to integrate simulation on the chip, including the transmission rate of the data interface, was also increasing simultaneously. This posed a challenge to the ATE at the time. "The older testbed was not actually able to cover the needs of the newly integrated analog and high-speed interface testing, so the functionality of ate needed to be enhanced. That is to say, at that time, ATE design and development had to meet the increasingly complex demand for SoC chips," Huang Feihong told reporters.
Between 2000 and 2015, the process became more and more advanced, the chip size became smaller and smaller, and the transistor integration on the chip became higher and higher. At this time, the chip's special design for testing, standardized interface and DFT design capabilities are also constantly strengthened. Because only by doing so can we cover the increasingly complex chip test requirements, including deeper and deeper SCAN testing, BIST testing, and standardized interface testing.
At the same time, because the scale of the chip has become larger, it has brought higher test costs, which requires the test to be pushed forward from the previous single station to the multi-station, which in turn brings the requirements of the same test. In other words, an important demand for testing in this era is that more and more channels can be integrated on the test machine board, and 2-station, 4-station, and 8-station tests can be done at the same time.
After entering 2020, the chip manufacturing process has shrunk to 5nm and continued to advance to 3nm, and the growth rate of chip crystal volume in this era has begun to exceed the limit of the device. In addition, the chip cycle of this era is shortened, and the complexity of the chip is also greatly improved, which makes the testing of chips enter the era of complexity. This brings a new round of challenges.
According to Huang Feihong, the evolution of advanced technology first brought about an increase in chip test time, which was partly caused by testing the number of transistors that exploded. As shown in the left of the figure below, if the test benchmark is taken in 2015, the time spent on the same test can now be close to 2.5 times that of that year, and it can even be further increased to three times in the future; in addition, for chips such as analog and RF, trim adjustments need to be made when doing testing, which in turn brings about an increase in test time. "The increase in testing time means higher test costs," Wong stressed.
He further pointed out that Wafer yield is another challenge posed by advanced processes.
As shown on the right side of the figure above, Huang Feihong told reporters that with the continuous reduction of the process size, wafer's initial lead continues to decline. More and more complex chips also increase the size of each chip, which in turn increases the probability of chip failure. Under the superposition of these two factors, the initial yield of the 800 square millimeter size wafer fell to less than 10%. But at the same time, our demand for chips is getting higher and higher.
"In the past, we were able to accept higher failures for consumer electronics chips, but as consumer and mobile chips moved to the automotive, our chip failure requirements have increased exponentially, which makes chip testing more difficult," Huang Feihong said.
Tereda's tricks
There is no doubt that Tereda is one of the leaders in the field of ATE, and over the past few years, they have also launched several leading devices for SoC testing, of which the J750 series is undoubtedly one of the representative products.
According to the data, the Teradyne J750 series provides the world's leading product test solutions for automotive and consumer applications MCU products, and is also a global leader in image sensor testing. With the growing level of integration of low-cost products and extending to fingerprint sensors, MEMS, and Internet of Things (IOT) products with MCU wireless capabilities, the scalability of the J750 test system makes it ideal for this type of product.
But as Huang Feihong said, the J750 is a chip with simple testing, and the pursuit is more of a low-cost solution. As a result, Tereda launched the UltraFLEX series to meet the needs of higher-level testing. UltraFLEX test systems use industry-leading software with the performance and precision needed to test complex system-on-chip (SoC) chips, significantly reducing test costs and speeding time to market.
As we can see from the official website introduction, the UltraFLEX series can provide mobile application processors, digital baseband processors, high data rate RF Transceiver, RF Connectivity chips, millimeter wave, 5G, power management chips (PMIC), microprocessors, network processors, high-speed SERDES (serializers/deserializers) and backplane transceivers, storage controllers, high-end microcontrollers, Testing of chips such as audio and video processors provides full support.
Although there is the UltraFLEX series, but with the increase in chip performance and variety, and put forward new requirements for testing, so Teradyra has launched a new UltraFLEXplus series, focusing on solving the emerging digital test needs brought by artificial intelligence and 5G communications.
According to Huang Feihong, the UltraFLEXplus series first increased the number of stations, and reduced the multi-station test time overhead by improving the efficiency of parallel testing, so as to meet the test cost requirements. Reducing the number of test cells minimizes total manufacturing costs, and fewer test cells translate into fewer probe stations and sorters, lower equipment power, and fewer operators.
Secondly, UltraFLEXplus's chip test interface board design has made completely revolutionary improvements, using Broadside technology, making the application area of the interface board larger, and at the same time making the interface board PCB layer less. According to official information, compared with the traditional ATE, the Broadside DIB structure rotates the board by 90 degrees compared with the original structure, so the resources of the board can be transmitted to the chip area in parallel. This means that each station can obtain a signal transmission path that matches it. Achieve faster time to market, more workstations, and higher PCB yields by simplifying otherwise complex DIB layouts.
Third, UltraFLEXplus also features a new PACE architecture to create the highest test cell capacity with minimal engineering effort. It is understood that the reason why PACE has achieved this result is mainly due to its distributed multi-controller (DMC) control architecture and the improvement of the data bandwidth of the board hardware. Multi-core system controllers increase system productivity by keeping boards efficient and coordinated. Increasing the number of workstations increases productivity and improves the efficiency of parallel testing, enabling manufacturers to reduce test cell deployments by 15%-50%.
Finally, Teradyne has maintained support for the IG-XL software for both the company's UltraFLEX and UltraFLEXplus series, which means that the programs developed by engineers can be easily and seamlessly migrated between the above devices, greatly reducing the development time of development engineers.
Huang Feihong also pointed out that the company has nearly 6,000 sets of UltraFLEX installed, UltraFLEXplus series since its launch in 2019, the global installed capacity has now approached 600 units, IG-XL software installation has exceeded 12,000 sets. The company has also trained more than 10,000 IG-XL program developers to prepare for future explosions of testing requirements.
Asked what kind of demand changes will be brought to future tests as the chip manufacturing process continues to evolve, Huang Feihong responded:
"The requirements for test equipment are two: the first is how to ensure the accuracy of the test under the higher data rate, which must be more and more stringent with the evolution of the process; the second is that as the process continues to evolve, the density of the integrated transistors in the chip is geometrically increased." The scanning volume is very long, even more than 1 G, which brings us the challenge of how to meet the increasing depth of storage vectors under each channel. This is why our plus generation of products can be scanned up to 19.2G through some technology. From the current point of view, even if it reaches 2 nanometers, 3 nanometers, or even further ahead, this vector depth can meet such a demand. ”
Huang Feihong pointed out that as the process continues to evolve to a trend in the future, the proportion of wafer tests will increase, and FT tests will decrease. This is mainly caused by the way the chip improves performance.
According to him, there are two ways for future process evolution technology, one is 5 nanometers, 2 nanometers, and 1 nanometers are constantly moving forward, but in fact, the difficulty of evolution is getting more and more difficult. The other is to take the Chiplet (core grain) route, that is, different modules in a chip do not necessarily need to use 2 nanometers and 3 nanometers per module chip, and some RF, analog, and mixed signals need 16 nanometers. In this case, putting a chip (Die) with different functions on the chip and then sealing it together means that after sealing, you can't do the relevant tests. That for the chip, the proportion of CP will increase, and the FT will decrease.
"In the future, there may be a new trend, that is, there is also a standard for communication interfaces after the sealing, how this standard goes to each die through the peripheral common channel access, there is no particularly good unified standard." If this standard comes out, it may also be accessed to each chip (die) through this way and then tested. Huang Feihong said.
At that point, we will be able to see how Tereda "moves" to deal with it.
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