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原部落格連結：https://blog.csdn.net/qq_38305370
原部落客昵稱：城外南風起
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Reset synchronizer可以實作異步複位同步釋放[1]。這種複位電路可以保留異步複位設計簡單的優勢，又避免了異步複位釋放時可能産生的亞穩态[2]。
圖源[1]。
Reset synchronizer代碼：
module asyn_rst_syn_release(
input clk,
input rst_n,
input data_in,
output reg data_out
);
reg rst_n_reg_a,rst_n_reg_b;
wire rst_n_sync;
always @ (posedge clk or negedge rst_n)
if (!rst_n)
begin
rst_n_reg_a <= 1'b0;
rst_n_reg_b <= 1'b0;
end
else
begin
rst_n_reg_a <= 1'b1;
rst_n_reg_b <= rst_n_reg_a;
end
assign rst_n_sync = rst_n_reg_b;
always @ (posedge clk or negedge rst_n_sync)
if (!rst_n_sync)
data_out <= 1'b0;
else
data_out <= data_in;
endmodule
簡單來說，Reset synchronizer在複位時與異步複位相同，但在複位釋放時，會把rst_n信号打兩拍，實作同步釋放。（這裡看不懂的話後面有testbench和波形）。
testbench：
`timescale 1ns / 1ps
module asyn_rst_syn_release_tb();
reg clk;
reg rst_n;
reg data_in = 1;
wire data_out;
initial
begin
clk = 1;
#200 $stop;
end
initial
fork
rst_n = 1;
#12 rst_n = 0;
#20 rst_n = 1;
//#32 rst_n = 0;
//#42 rst_n = 1;
#112 rst_n = 0;
#114 rst_n = 1;
//#132 rst_n = 0;
//#138 rst_n = 1;
join
always #10 clk =~clk;
asyn_rst_syn_release asyn_rst_syn_release0(
.clk(clk),
.rst_n(rst_n),
.data_in(data_in),
.data_out(data_out)
);
endmodule
波形：
可以看到，rst_n = 0時，立即觸發異步複位，data_out = 0；而當rst_n重新置高後，打了兩拍才同步釋放，這時，rst_n_sync已經穩定在高電平了，此時采樣就不會出現亞穩态的問題。
這也是為什麼需要兩個寄存器，如果隻打一拍，rst_n_sync置高時剛好發生在clk上升沿，此時可能會發生亞穩态。關于這一點，Clifford E.Cummings在論文中是這樣解釋的：[1]
The first flip-flop of the reset synchronizer does have potential metastability problems because the input is tied high, the output has been asynchronously reset to a 0 and the reset could be removed within the specified reset recovery time of the flip-flop (the reset may go high too close to the rising edge of the clock input to the same flip-flop). This is why the second flip-flop is required.
The second flip-flop of the reset synchronizer is not subject to recovery time metastability because the input and output of the flip-flop are both low when reset is removed. There is no logic differential between the input and output of the flip-flop so there is no chance that the output would oscillate between two different logic values.
代碼RTL電路：
最後，我産生了一個問題，按這樣來說，當複位釋放在clk上升沿附近時，同步複位是否也會産生亞穩态？這個問題在[1]中同樣有答案：
A different but similar problem exists for synchronous resets if these spurious reset pulses occur near a clock edge, the flip-flops can still go metastable (but this is true of any data input that violates setup requirements).
When a synchronous reset is being used, then both the leading and trailing edges of the reset must be away from the active edge of the clock.
參考：
[1]Clifford E.Cummings, Don Mills, and Steve Golson. Asynchronous & Synchronous Reset Design Techniques - Part Deux[C]SNUG (Synopsys Users Group) 2003User papers
下載下傳：http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf
[2]EDA先鋒工作室編著.輕松成為設計高手 Verilog HDL實用精解[M].北京航空航天大學出版社,2012.
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