问题描述：在Vivado生成bit流文件时，编译出现问题。
Resource utilization:LUT as Distributed RAM over-utilized in Top Level Design
问题解决：可以尝试使用URAM来解决BRAM不够用的问题，从而解决LUT资源的紧张（LUT as Distributed RAM）
从Vivado的报告可知，对URAM的利用率为零，那么如何充分利用URAM呢
Arrays on the Interface
在Vivado IP flowVitis HLS中，默认情况下将数组合成为内存元素。当使用数组作为顶级函数的参数时，Vitis HLS假定以下情况之一
1.Memory is off-chip
2.Memory is standard block RAM with a latency of 1
To configure how Vitis HLS creates these ports:
• Specify the interface as a RAM or FIFO interface using the INTERFACE pragma or directive.
• Specify the RAM as a single or dual-port RAM using the storage_typeoption of theINTERFACE pragma or directive.
• Specify the RAM latency using the latencyoption of the INTERFACE pragma or directive.
• Use array optimizationdirectives, ARRAY_PARTITION, or ARRAY_RESHAPE, to reconfigurethe structure of the array and therefore, the number of I/O ports.
Array Interface
如果没有明确storage_type,Vitis HLS使用：
- A single-port RAM by default
-
A dual-port RAM if it reduces the initation interval or reduces
latency
pragma HLS bind_storage
描述：
BIND_STORAGE pragma将代码中的变量(数组或函数参数)赋给RTL中的特定内存类型(type)。
这种用法对于顶级函数接口上的数组很重要，因为与数组关联的内存类型决定了在theRTL中需要的端口的数量和类型，如接口上的数组所讨论的
语法：
#pragma HLS bind_storage variable=<variable> type=<type>\
[ impl=<value> latency=<int> ]
type=<type>: Defines the type of memory to bind to the specified variable.
Supported types include: fifo, ram_1p, ram_1wnr, ram_2p, ram_s2p, ram_t2p, rom_1p, rom_2p,rom_np.
impl=<value>: Defines the implementation for the specified memory type.
Supportedimplementations include: bram, bram_ecc, lutram, uram, uram_ecc, srl, memory, andauto as described below.
latency=<int>: Defines the default latency for the binding of the type.
As shown in thefollowing table, the valid latency varies according to the specifiedtype and impl. The defaultis -1, which lets Vitis HLS choose the latency
Example
the coeffs[128] variable is an argument to the top-level functionfoo_top. The pragma specifies that coeffs uses a single port RAM implemented on a BRAM