TSMC pointed out in its 2023 annual report that TSMC's 2nm R&D focuses on basic process formulation, yield improvement, crystal and wire efficiency improvement, and reliability evaluation, and it is expected that in 2024, important customers will complete chip design and begin verification.
Intel is vice president said in an interview that Intel's 20A, or 2nm process, will enter mass production in 2024, and Intel is ready to lead the miniaturization again, of which Arrow Lake is the leading product, which is expected to be launched in the second half of 2024.
Samsung, on the other hand, said in its financial report that its foundry will officially launch SF2, that is, the 2nm process in June, and the PDK, EDA tools and licensed IP of SF2 will be completed in the second quarter of 2024, and then partners will be able to use SF2 to design and manufacture chips.
All three foundries see the launch of 2nm as a major event, but we still have questions: what exactly can 2nm be used for? To what extent can it change current chips?
Recently, TSMC Executive Vice President and Co-COO Yujie Mi and AMD CTO Mark Papermaster had a conversation about 2nm, which may help us gain a deeper understanding of 2nm and the world beyond.
The boundaries between physics and innovation
In this conversation, TSMC COO Mi Yujie first mentioned the difficulty of 2nm, TSMC started from 0.5 microns to 2nm, in more than 30 years, the transistor scaling has exceeded 4000 times, but with the upgrading of the process, the expansion has become more and more challenging, but he believes that there is still room for development after 2nm, and the key to success is customer cooperation.
TSMC adopts a dual R&D team system, through two teams to launch the latest process alternately, with more time and technical resources, although the current development cycle of each generation of the process is as long as five or even seven years, which is significantly slower than the previous two to three years, but it has not stopped. He emphasized that after the 7nm process, TSMC will introduce new technologies in each new process, and 2nm will introduce more complex GAAFET technology, which is tentatively scheduled for mass production in 2025.
He also mentioned that TSMC is developing technologies, including silicon photonics, working with DRAM suppliers to optimize HBM, and working on CFET transistor schemes that stack n and p MOS devices on top of each other. TSMC will conduct more development in the future to keep the semiconductor industry moving forward.
AMD's chief technology officer, Peppermaster, also put forward his own views on the current advanced process, he said that since the early 2010s, the cooperation model between traditional foundry and fabless IC design enterprises has gradually revealed its shortcomings, and in the current foundry market, Party A and Party B need to reach closer cooperation, and everyone works together to make the chip play its due performance.
Peppermaster believes that TSMC is emphasizing the increasing role of Design-Technology Co-Optimization (DTCO). On the one hand, DTCO can help identify process routes that are too extreme and lack value, focus on customers' real needs, and reduce development pressure, on the other hand, DTCO can help customers strike a balance between the three major factors of product performance, energy consumption, and chip area, and achieve the goal that is difficult to achieve with process scaling alone. DTCO also helps unleash the technical potential of a single node.
Peppermaster's DTCO, which many people may not know enough about, is a mysterious method that has played an important role in improving the performance of TSMC's advanced processes over the past few generations.
DTCO is the collaborative optimization of design technology, as its name suggests, that is, the design and process technology seek integrated optimization to improve efficiency, power efficiency, crystal density, and cost, TSMC has previously said that the process R&D team and the design R&D team must work together at the beginning to carry out design technology collaborative optimization for the definition of the next generation of technology, and the two teams must keep an open mind and explore the possibility of design innovation and process capabilities, and many innovative ideas are put forward at this stage. Some of these ideas may be too positive to be realized with existing technologies, and some ideas may seem promising at first but turn out to be less practical, and the purpose of design technology co-optimization is to define truly meaningful adjustments that go beyond mere geometric scaling to achieve the goal of improving performance, power, and area.
For example, TSMC's 7nm is one of the proofs of the success of co-optimization of design technology. It is the first to adopt a fin-field-effect (FinFET) transistor structure at 16nm, using a three-fin structure on a single standard element, providing better driving strength than planar transistors. Based on the characteristics of fin separation, the first generation of FinFET technology maximizes the placement flexibility of fins by using a global fin grid that pre-sets the position of the fins, and is a universal fin grid system that supports logic and hybrid new designs across the entire chip.
As we move to 7nm, TSMC found that general-purpose fin grids may not be the best choice for optimizing performance, power consumption, and area, so it introduced the concept of a local fin grid when exploring collaborative optimization of design technologies, creating the flexibility to optimize the placement of standard component fins and minimize parasitic capacitance and resistance. As a result, we were able to use fewer fins to achieve the required performance while increasing density than the previous generation process. Compared with the 10nm process, DTCO increases the logic density of TSMC's 7nm process by more than 1.6 times, increases the speed by about 20%, and reduces power consumption by about 40%.
DTCO's holistic view of how devices interact with each other and how they meet multiple requirements at the same time has prompted foundries to look for new ways to build devices, and it has been a key factor in the transition from planar transistors to finFETs, and the engineering experience gained from finFETs has been the enabler of full-gate nanosheet transistors and future fork transistors and CFETS.
It's when traditional scaling methods start to fall short that DTCO really starts to get taken seriously. By co-optimizing design and technology, system and technology, system architects can gain more advantages from technology than traditional scaling methods, siloed design and process steps need to evolve into cross-functional teams, and extensive collaboration has been recognized as the key to driving semiconductor development, with the introduction of GAA, the importance of DTCO has become more prominent.
As a technician of a chip design company, Peppermaster and Mi Yujie from the wafer foundry reached a consensus in this regard: the 2nm and even more advanced processes are no longer behind closed doors in the wafer foundry, but need the help of more design companies.
Powered by Chiplets
AMD also offers a new perspective on chip technology after 2nm in a separate video, where AMD CTO Peppermaster and AMD senior vice president and corporate researcher Sam Naffziger discuss how chiplets can challenge the slowdown of Moore's Law by breaking down semiconductors into components assembled in novel ways, and perhaps help the semiconductor industry at 2nm and beyond.
Both Peppermaster and Nafziger emphasized the importance of chip standardization.
"Domain-specific accelerators are the best way to achieve the best performance per watt and dollar. So that's absolutely critical for making progress," Nafzig explained, "You can't have a specific product for every space, so what we can do is build a chip ecosystem – essentially a library." ”
Nafzig was referring to Universal Chipset Interconnect Express (UCIe), an open standard for chipset communication that has won widespread support from giants including AMD, Arm, Intel, and Nvidia since its inception in early 2022, and is being attempted by small and medium-sized businesses.
AMD has been at the forefront of chipset architecture since the introduction of the first generation of Ryzen and Epyc processors in 2017. Today, Zen's chip library has grown to include multiple compute, I/O, and graphics chips, which are packaged into consumer and data center processors. One example of a chipset is AMD's Instinct MI300A APU, which was launched in December 2023 and contains 13 separate chips – 4 I/O chips, 6 GPU chips, and 3 CPU chips, as well as 8 sets of HBM3 memory.
Nafziger said that in the future, standards like UCIe could bring third-party manufactured chipsets into AMD's packages, citing silicon photonic interconnects, a technology that can alleviate bandwidth bottlenecks and potentially bring third-party chips to AMD products in the future. However, he also believes that silicon photonic interconnects are not feasible without low-power chip-to-chip interconnect technology.
"You're mounting optics on chips because you need huge bandwidth," Nafzig said. So you need a relatively low power consumption per bit for that to make sense, and the chip in the package is the way to get a low-power interface. He believes the shift to co-packaged optics is "coming."
To this end, several silicon photonics startups are already launching such products. For example, Ayar Labs has developed a UCIe-compatible photonic chipset that was integrated into a prototype of Intel's graphics analytics accelerator manufactured last year, but as of now, third-party chips (whether photonic or otherwise) have yet to make their way into AMD products, and standardization is just one of the many challenges that need to be overcome to achieve heterogeneous multi-chips.
It's worth mentioning that AMD has supplied chipsets to rival chipmakers in the past, and Intel's Kaby Lake-G part introduced in 2017 features Chipzilla's eighth-generation cores and AMD's RX Vega GPUs, which recently appeared on Topton's NAS boards.
Nafziger has also previously been interviewed by IEEE Spectrum, where he also gave his opinion on how chiplets are changing the semiconductor manufacturing process.
"It's definitely something that the industry is grappling with. That's where we are today, and that's where we're probably going in 5 to 10 years. I think the technologies these days are basically general-purpose, and they can be well matched to monolithic chips, and they can also be used for chipsets. For chips, we have more professional intellectual property rights. As a result, we can envisage the specialization of process technology in the future and reap performance benefits, cost reductions, and other benefits. But that's not the current state of the industry. Nafzig said.
Nafzig said that one of the goals of AMD's architecture is to make it completely transparent to the software, and that AMD is currently looking for ways to extend the logic capabilities, but SRAM is a bigger challenge, and the analog capabilities certainly can't be extended. AMD has already taken steps to separate analog from central I/O chips, such as 3D V-Cache, a high-density cache chip that is three-dimensionally integrated with the compute chip, and he hopes there will be more of these specialized products in the future.
In today's slowdown of Moore's Law, chiplets can help AMD realize more technical visions, even after the process is advanced to 2nm, chiplets can help solve pain points such as SRAM, so far, standardization is a problem that chiplets need to solve urgently.
Write at the end
The battle for 2nm has now quietly begun, TSMC, Intel and Samsung began to find their own customers, tens of billions of dollars smashed into new fabs, the first manufacturer to mass-produce 2nm chips, will undoubtedly lead the process revolution later.
However, for fabless companies like AMD, the expensive advanced process of 2nm is not only to increase the transistor density of the chip, but also to take into account the future architecture evolution, as well as the convergence and integration of advanced packaging and other technologies, how to weigh the process of 2nm and even 1.6nm, and pose new problems to the chip design industry in the future.
[Source: Semiconductor Industry Observation]