As the speed of transistor size scaling in chips slows down, a key technology for integrating system functions is emerging: heterogeneous integration (HI).
It utilizes advanced packaging technology to achieve higher functional density and lower cost/function ratio. With the rapid development of major semiconductor applications such as high-performance computing (HPC), edge AI, autonomous driving, and electric vehicles driven by AI large models, traditional complex logic chips are changing to chiplets with smaller size and finer functional divisions, which puts forward higher requirements for chip-to-chip interconnect, including higher density, faster speed, and higher reliability. This has dramatically increased the need for heterogeneous integration, which in turn has increased the demand for innovation in advanced packaging technologies.
Heterogeneous integration uses advanced packaging processes to integrate chiplets (chips) with heterogeneous designs and different process nodes into a single package, so that chip designers can choose the best process node according to their specific system needs, such as computing chiplets using 3nm process and RF chiplets using 7nm, so as to quickly design and manufacture superchips that can meet specific functions in a cost-effective manner. Heterogeneous integration not only targets higher interconnect density, but also integrates the various modules (e.g., logic chips, sensors, memories, etc.) required to achieve full system functionality in a single package. This approach can significantly improve overall efficiency and performance, while at the same time significantly reducing the package size.
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Advanced packaging solutions for AI HPC
Typical high-density advanced packages for high-performance processors for AI-accelerated and cloud computing applications are 55mm x 55mm or larger, typically containing 5-2-5 (top 5 layers, middle 2 layers, bottom 5 layers) advanced substrates, and some up to 11-2-11 lead layers. Chiplets can be interconnected via silicon bridge fan-out technology or via a 2.5D interconnect with a silicon interposer as an integrated platform. With these technologies, the industry aims to gain more computing power in the same space.
The high-density packaging solutions offered by ASE include flip chip ball grid array (FCBGA), fan-out chip-on-substrate (FOCoS), FOCoS-Bridge and 2.5D packaging. The interconnection between the chips in FCBGA is done through BGA substrates, and its minimum L/S (line width/line spacing) can reach about 10μm/10μm. TSMC's CoWoS (Chip on Wafer on Substrate), which is currently very popular and in demand, is a 2.5D packaging technology that uses RDL (redistribution layer) on a silicon interposer to connect chiplets, and its L/S can be as low as 0.5μm/0.5μm.
If you want to know more about TSMC CoWoS and advanced packaging process technology, please click to view:
· TSMC vs. Intel's chiplet and advanced packaging strategies are https://mp.weixin.qq.com/s/-8FT0SBPlkbEaxwS7FB_xQ
· TSMC's CoWoS advanced packaging capacity in the next two years has been bought out by Nvidia and AMD
https://mp.weixin.qq.com/s/vuIZuDiirYAinZ1stiE-KQ
In the silicon interposer of a 2.5D package, all chiplets are connected side-by-side. However, as the number of chiplets required increases, their area becomes larger and larger, resulting in a smaller number of chips that can be produced per wafer (12-inch wafers typically produce less than 50 dies), which significantly increases the manufacturing cost of 2.5D packages. However, not all applications require a fine pitch of 0.5μm/0.5μm, so ASE has proposed FOCoS, which uses fan-out technology to integrate different chiplets with L/S as low as 2μm/2μm, which provides the market and customers with a lower cost alternative solution.
In addition, ASESO's FOCoS-Bridge technology uses silicon bridges to interconnect different chips (such as logic chips and memories) to provide high-density cabling in areas where high-speed transmission is required, while Fan-Out RDL is used for integration in other areas. As a result, it combines the flexibility of 0.5μm/0.5μm and 2μm/2μm in the L/S design, while achieving significant improvements in packaging density and bandwidth.
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High-performance chip-package-system co-design
To achieve these goals of high bandwidth and high density, the chip-level, package-level, and system-wide level must be co-designed to optimize the overall design, rather than just individual levels or components. When EDA tools perform design optimization, they must consider the overall signal variation along the entire transmission path, including copper pillars, RDL fine lines, through-silicon vias (TSVs), microbumps, and more. The eye diagram can then be used to analyze the electrical performance of the SerDes link. When designing differential pairs for high-speed signals, there is a need to reduce return loss and insertion loss, especially in the operating frequency band. From the chip to the package to the entire system, Taiwan's manufacturing strength lies in the ability to complete a turnkey design process from start to finish.
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More computing power with less energy
The current focus of the chip design industry is on optimizing energy efficiency. One of the key questions that has been raised is whether the power conditioning and decoupling components that were previously on the system board can be moved closer to the package or processor chip. There are even proposals to redesign the on-chip power delivery network (PDN), such as directly from the back of the chip (Backside PDN).
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Power integrity design for power delivery networks (PDNs).
By strategically placing capacitors, you can optimize power integrity and minimize noise. Ideally, the capacitor should be placed as close to the chip as possible, but this depends on the size of the capacitor and the manufacturing process, both of which can affect cost and performance. Conventional SMT capacitors (surface mount) are relatively large, and chip-scale silicon capacitors (Si-Cap) can now be used to achieve very good capacitance characteristics.
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UCIe Alliance
Historically, system designers have had a number of standard communication protocols to choose from at both the chip and board levels (e.g., Block-to-Block, memory bus, or interconnect protocols). Industry protocols for package-level integration are evolving, especially considering the need for a common interface for chiplet integration using 2.5D and FOCoS packaging technologies.
In March 2022, Intel invited upstream and downstream manufacturers in the semiconductor industry chain to form the UCIe Alliance and launched a standardized data transmission architecture integrated with chiplet to reduce the cost of advanced packaging design. ASE is proud to be one of the founding members (founding members).
Headquartered in Taiwan, ASE is able to offer a wide range of advanced packaging types and develop package design specifications that are compatible with foundry specifications and can also be combined with the system requirements of OEMs and cloud service providers to meet the full range of UCIe packaging standards. The standard can assist in the implementation of various advanced packaging technology architectures, such as 2.5D, 3D, FOCoS, Fan-out, EMIB, CoWoS, etc., to meet the heterogeneous integration requirements of various chiplets in HPC applications. ASE is actively involved in the development and compliance of international standards in order to provide integrated solutions to the global semiconductor industry.
Heterogeneous integration technology has been developed for many years and can be used not only for the integration of homogeneous and heterogeneous chiplets, but also for the integration of other passive and active components such as connectors into a single package. Achieving such heterogeneous integration goals requires not only advanced packaging technology, but also coordination of design and testing. ASE can provide comprehensive design and packaging service solutions, including system design, packaging and test, to help customers shorten chip design cycles and accelerate product innovation.
