There are two main ESD protection applications of NMOS: one is GGNMOS as mentioned earlier, and the other is GCNMOS (Gate Coupling NMOS). Bulk Coupling NMOS has also appeared at this stage, and both ESD protection devices will be explained next.
The working principle of GCNMOS is different from GGNMOS, which uses the opening of a bulk parasitic transistor to discharge ESD electrostatic current, while GCNMOS uses the channel of the NMOS device as the bleeding channel. There are two ways for GCNMOS to turn on the NMOS tube: one is to use the electrostatic frequency as the trigger condition, and the other is to use the electrostatic voltage as the trigger condition, as shown in the figure.
图一.电压触发GCNMOS。
图二.频率触发GCNMOS。
The ESD design for components focuses on the protection of the chip in non-normal operating conditions. Therefore, the on-chip ESD design is to prevent the ESD device from interfering with the normal operation and ensure that the ESD electrostatic discharge channel can be generated when the static electricity comes, and the coupling method of the two is based on this core idea.
Voltage Triggering:
Under normal operating conditions, the differential voltage of VDD-VSS is less than the on-voltage of Zener or diode string, and the gate voltage of NMOS is low and NMOS is turned off. When an ESD current is generated on the VDD, this current is concentrated at the anode of the diode string or the cathode of the Zener tube until the voltage is sufficient to turn on the device. ESD current can be compared to water flow, ESD current always has to complete the drain, and will continue to accumulate and generate voltage before the leakage, until the internal device breaks down to generate a path or the ESD protection device opens a generation path. This feature is used to adjust the on-voltage Von of the Zener or diode string so that VDD<Von < Vbreak down. The voltage that turns the diode on should be greater than the normal operating voltage and less than the failure voltage of the internal device.
Frequency Triggering:
The frequency characteristics of the RC circuit distinguish the high-frequency ESD current from the normal power-on waveform. The waveform of the ESD is shown in the figure.
Figure 3. HBM waveform.
There will be a rising edge in the waveform of HBM within 0~10nm, and after reaching the peak, it will decay to about 20% of the peak in 150ns, and the duration of the entire ESD pulse is about 1us. In order to facilitate the understanding and systematic design, the time-domain waveform of HBM is converted into a frequency-domain waveform, as shown in Figure 4.
Figure IV. Frequency domain of the HBM waveform.
(This is just for the sake of illustration below, but the real transformation is much more complicated than that.) The energy in the HBM waveform is mainly concentrated in the first 20ns, and the sine wave transformed in this frequency domain is also the focus of attention, let this frequency range be ωESD. Frequency-triggered GCNMOS works by using the frequency response characteristics of RC circuits to respond to ESD waveforms. When the electrostatic waveform is generated on the VDD rail, the equivalent circuit of the RC part is shown in Figure 5.
Figure V. ESD-RC equivalent circuit.
The impedance of the capacitor is 1/jωC, then the main energy of HBM is concentrated in the high-frequency part, its equivalent impedance is small, the voltage drop is mainly concentrated in the resistor, the potential of point A is high, when the voltage is greater than the threshold voltage of NMOS, the channel is opened, and there is an electrostatic current discharge channel from VDD to GND. When the ESD frequency ends, the intrinsic response of RC will also cause NMOS to continue to be on for a period of time, ensuring that NMOS remains on throughout the ESD event. When powered on normally, the equivalent circuit is shown in Figure 6.
Figure VI. POWER-ON-RC equivalent circuit.
The power-on speed of the general circuit is much lower than the ESD discharge frequency, at this time, the capacitor impedance is large, the voltage is concentrated on the capacitor, the potential of point A is low, and the NMOS is turned off, which will not affect the normal operation. The current design also has the position of the capacitor resistor reversed as shown in Figure 2(b), and its basic principle is the same as that of CR, but it is necessary to add an inverter to the circuit, and this inverter can not only change the potential, but also reduce the area of R and C by changing its structure to increase the gate voltage of the NMOS of the next stage.
For example:
图七. SRAM ESD power clamp电路图
图八. SRAM ESD power clamp仿真结果。
This is an example of CR voltage trimming using SRAM results, and the circuit diagram and simulation results are shown in Figures 7 and 8. It can be seen that VM2 does not need to be very high all the time due to the SRAM results, and the time constant τ of CR is very low, which means that the area of C and R does not need to be large.
A shut-down control circuit will also be added to the current GCNMOS circuit to realize the function of open circuit or short circuit GCNMOS after the chip is powered on. This is also related to the design idea of component ESD, and the protection scenario of component ESD is only for the static electricity of the chip when it is not in use. However, without shut-down control, there may be a false trigger situation where GCNMOS is turned on when facing the system ESD after the chip is powered on.
Compared with GGNMOS, GCNMOS has the advantage that it can effectively reduce the influence of parasitic parameters and is widely used in high-speed occasions, but its area requirement is also large, and it cannot be applied to complex occasions such as high voltage and negative pressure.