Achronix has a long history of providing innovative FPGA products and technologies for data-intensive and high-bandwidth applications in a variety of industries, helping customers push the limits of performance. Some of these applications require interfacing with advanced analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) – a task that JESD204C can do perfectly.
JESD204B/C is a serial interface standard for high-speed data converters defined and developed by JEDEC. This standard reduces the number of data inputs and outputs between high-speed data converters and other high-performance devices such as Achronix Speedster7t FPGAs. This combination of digital and analog signal chains benefits designers by enabling them to achieve a simplified small form factor board layout without adversely affecting the performance of the end system. Interfaces/interconnects between data conversion devices are implemented through high-speed general-purpose I/O (GPIO) or SerDes channels.
Achronix has implemented JESD204C interfaces on its Speedster7t FPGA devices, enabling customers to use the ADC or DAC of their choice. Thanks to the soft JESD204C interface implemented on a homogeneous FPGA architecture, customers can use their preferred ADC/DAC devices and customize their designs. This article discusses JESD204C solutions based on Achronix Speedster7t FPGA devices.
The Achronix JESD204C solution supports all of the features mentioned in the standard and improves on previous versions. It aims to achieve all four objectives set forth by the standards body:
• Increase lane rates to support the higher total bandwidth required – Achronix's solutions currently support data rates of up to 24.75 Gbps per SerDes lane. SerDes can support JESD204C-capped lane rates of 32 Gbps. The data converter used for the test design uses the AD9082 from Analog Devices (ADI), which supports a maximum data rate of 24.75 Gbps.
• Improved payload transfer efficiency – Achronix users can use FPGA logic to customize and optimize their designs.
• Link Robustness – Achronix's solutions demonstrate high robustness in single-channel and multi-channel mode links while maintaining deterministic latency. For example, for those modes that do not have a quantification effect, the sampling rate can reach the highest limit supported by the AD9082.
• Backward compatibility with previous JESD204B versions – Achronix will provide JESD204B solution.
Laboratory testing protocols
Achronix has successfully implemented and demonstrated the Speedster7t JESD204C solution for ADI's AD9082, which has a quad 16-bit DAC and a dual 12-bit ADC converter. The experimental loopback setup (shown in Figure 1) includes the following components:
• Bittware's VectorPath S7t-VG6 accelerator card. The board uses an Achronix Speedster7t FPGA device.
• Connects VectorPath to ADI's EVAL-AD9082 connector. Achronix has developed a 4-lane QSFP-to-FMC connector that can be adjusted to 8 or 16 channels if required.
• ADI EVAL-AD9082 ADC/DAC board with FMC connector.
• Required test equipment and other accessories.
Figure 1: The EVAL-AD9082 connector board connecting VectorPath to ADI
The experimental setup provides a complete signal chain in both transmit (Tx) and receive (Rx) directions. The functions of each component are as follows:
• Implement JESD204C transmit/receive IP functionality in the Speedster7t AC7t1500 FPGA device on the VectorPath accelerator card. Run specific test scripts through the Linux console on the connected PC.
• The Speedster7t SerDes channel connects to the ADC/DAC via a custom FMC-QSFP connector board. The QSFP28 module supports four SerDes lanes, each running at 24.75 Gbps.
• Thousands of registers on ADI's AD9082-FMCA-EBZ evaluation board can be programmed through the API call from the connected PC. Alternatively, the registers can be programmed using the soft CPU cores on the FPGA or the hard CPU cores in the SoC.
• An external clock source synchronizes the VectorPath accelerator card with the AD9082-FMCA-EBZ evaluation board. An internal clock can also be generated by using an oscillator on the AD9082-FMCA-EBZ and fed to the VectorPath accelerator card via an FMC-QSFP connector.
• Waveforms generated by an Arbitrary Waveform Generator (AWG) are externally transmitted directly to ADC0 and ADC1.
• Loopbacks occur inside the Speedster7t FPGA, between the JESD204C receive and transmit modules, while the DAC output is displayed on the oscilloscope.
•The expected waveforms for the DAC0 and DAC1 outputs are displayed on the connected oscilloscope.
Figure 2: Example of a four-channel loopback
The diagram above shows a four-channel loopback configuration. The signal path is AWG (I/Q signal) → AD9082-FMCA-EBZ (ADC) → FMC QSFP56→ Speedster7t JESD204C Rx→ loopback→ Speedster7t JESD204C Tx→FMC QSFP56→ AD9082-FMCA-EBZ (DAC) → oscilloscopes.
The input I/Q waveforms of ADC0 and ADC1 of the AD9082-FMCA-EBZ have the same frequency but are 90 degrees out of phase. The frequency depends on the mode supported by the AD9082-FMCA-EBZ, which can be set to achieve the highest frequency declared by that particular mode with minimal and acceptable jitter.
Based on the Speedster7t FPGA device, the advanced Achronix JESD204C solution achieves the highest rates supported by JESD204C data converters. The solution provides a vendor-agnostic interface to connected ADC/DAC devices, allowing customers to choose their preferred ADC/DAC vendor.