According to AnandTech, the US chip software design tool giant Synopsys (Synopsys) launched the industry's first full-stack AI-driven electronic design automation (EDA) tool suite Synopsys.ai, covering all stages of chip design from architecture to design and implementation to manufacturing.
The kit is expected to radically reduce chip development time, reduce design costs, increase throughput, and enhance chip performance. This set of tools will shorten the development time of chipsets manufactured at cutting-edge nodes (such as 5nm, 3nm, 2nm, etc.) and maintain or even reduce chip development costs.
First, the cost of chip development exceeds 1 billion US dollars, and the software cost accounts for 40%
As the complexity of chip design increases and process technology continues to iterate. Its design and manufacturing costs have risen to unprecedented levels. Designing a complex 7nm chip costs about $300 million, including about 40 percent of the software overhead. According to International Business Strategy (IBS) estimates, a 5nm chip including software costs more than $540 million to design. The development cost of a complex 3nm GPU is about $1.5 billion, including about 40% of the software expenses.
▲Chip development cost (Source: AnandTech)
The drawbacks of traditional semiconductor design methods may be one of the reasons for the sharp rise in chip development costs. It requires hundreds of engineers and thousands of servers to develop and simulate architecture, structure, logic, and layout designs over several years. At the same time, each design stage is critical to the quality of the chip, but these tasks are inherently iterative and time-consuming.
For this reason, as chips become more complex, semiconductor companies cannot arbitrarily assign a large number of engineers from a limited number of employees to a task, so each design takes longer and longer.
▲Traditional "waterfall" chip design method (Source: AnandTech)
The waterfall approach virtually excludes backward flow, choosing one of thousands of possible layout designs with little impact on the architectural design. Therefore, the only way to avoid inefficiencies that lead to higher than expected costs, lower performance than expected, and higher power consumption than expected is to bring different design teams closer together at all stages. However, this becomes more difficult as the design cycle lengthens.
The manufacturing cost of 5nm and 3nm chips is also significantly higher than the cost of the previous generation of chips. The latest manufacturing processes require extensive use of extreme ultraviolet lithography and more expensive raw materials (e.g., photomask particles, resists, etc.). Therefore, for chip developers, achieving near-perfect designs and lower costs becomes even more critical.
Overall, the semiconductor industry today faces several challenges, namely reducing development time, maintaining or even reducing chip development costs, and ensuring predictable manufacturing costs. With the industry facing a shortage of highly skilled engineers, all circumstances have to be taken into account, and this is where Synopsys.ai EDA suite comes into play.
Second, the Synopsys software suite can be used in the whole stage of chip design
Synopsys.ai full-stack EDA kit consists of three key applications: DSO.ai for chip design; Synopsys VSO.ai for functional verification; TSO.ai for silicon testing. The kit is designed to leverage CPU- and GPU-accelerated machine learning and reinforcement learning to accelerate iterative and time-consuming chip design phases.
Stages covered by Synopsys software (Source: AnandTech)
It's been two years since Synopsys launched its AI-powered DSO.ai, and to date, more than 100 designs have been completed using the EDA tool.
Synopsys software suites can be used in all chip design phases, including simulation, design capture, IP verification, physical implementation, signoff, test, and manufacturing. The company wants to fast-track all design stages with artificial intelligence.
Third, artificial intelligence finds the optimal solution as quickly as possible to help improve microarchitecture development capabilities
Experienced engineers typically develop microarchitectures, a phase considered by many to be the intersection of technology and art. In fact, the development of microarchitectures is also quite fast. Synopsys believes that this stage can be accelerated and improved with artificial intelligence, because machines are different from humans, and machines can quickly estimate the most efficient architecture parameters and data paths.
Shankar Krishnamoorthy, General Manager of Synopsys Electronic Design Automation (EDA), said, "The entire process of developing a chip starts with the architecture of the chip and has many aspects to consider. How much space does the cache need? What kind of interface is there between the computer and the memory? What memory configuration should be considered, these create many choices, and an architecture expert will quickly explore these options and then converge on what are the right parameters to implement the chip design. This process can be used by artificial intelligence to quickly explore solutions and produce a better result. ”
In a shortage of experienced architects, using AI for microarchitecture exploration can improve a company's microarchitecture development capabilities.
Krishnamoorthy also said: "AI is really a good assistant when there is already an expert. Modern AI techniques use reward and punishment mechanisms to select a more appropriate architecture in a very large parameter space. The result is several options, such as power and performance trade-offs, from which the architect can pick and choose the most appropriate workload choice. ”
Fourth, speed up the IP verification process, VSO.ai can increase the verification productivity by 30%.
Functional and IP verification is a time-consuming chip design step. Chip designers need to test each IP individually and make sure it functions correctly before integrating it, and when multiple IPs are combined, the complexity of verification increases exponentially. At the same time, it is essential that each individual IP achieves a high level of test coverage.
▲VSO.ai function (Source: AnandTech)
Now, a common way to verify IP is for designers to create a test baseline that reflects their verification strategy, and then, with the help of a traditional simulator, simulate that test baseline using traditional simulation techniques, such as constrained stochastic simulation. Achieving high target coverage for specific IPs faster is a challenge that Synopsys VSO.ai can solve, and it's part of the Synapsys.ai.
"By digging technologies such as reinforcement learning into the simulation engine, 99% coverage of IP can be achieved while target coverage can be achieved in less time," said the EDA group leader at Synopsys. Synopsys VSO.ai software can both expand target coverage and speed up the IP verification process. ”
Takahiro Ikenobe, director of IP development for the core IP division of Japanese semiconductor chip giant Renesas Technologies, said, "Due to the rise in design complexity, it is becoming difficult for chip designs to use traditional technologies to meet quality and time-to-market constraints. Using Synopsys VSO.ai's AI-driven verification, we have achieved up to 10x improvements in reducing functional coverage holes and a 30% increase in IP verification productivity, demonstrating AI's ability to help us meet the challenges posed by increasingly complex designs." ”
5. Quickly complete the layout and winding, and DSO.ai the number of design chips is as high as 170
It is very difficult to complete complex chip designs in the real world. While EDA tools are responsible for the chip design process, skilled human engineers are still required to complete chip layout planning, winding wires, and use their experience to create efficient designs.
Although experienced engineers work quickly, they have limited ability to quickly evaluate hundreds of design options in a reasonable time frame, explore all potential combinations, and simulate dozens or even hundreds of different layouts to determine the best design. Usually they will use the best methods, but these methods may not be the most efficient for a particular chip manufactured at a particular production node.
▲DSO.ai function (Source: AnandTech)
Instead of simulating all possible chip layouts and winding methods, platforms such as DSO.ai leverage AI to evaluate all combinations of architecture choices, power, and performance targets, and then simulate different layouts to find a layout that meets the expected performance, power, area, and cost (PPA) combinations in a short period of time.
It is quite difficult to simulate a real CPU and GPU in the simulation link. Traditionally, chip designers have used large CPU- or FPGA-based machines to emulate future chips. However, Synopsys applied GPU acceleration to these workloads and achieved several times the performance gains.
"If we look at discrete memory designs, such as DRAM or NAND flash, these are very large circuits that need to be simulated for electrical correctness, physical correctness, but also to account for pressure, IR drop and all other types of effects," Krishnamoorthy said. Simulating these very large discrete memory structures is time-consuming. This is an area where we have successfully applied GPU acceleration to accelerate several times the speed up of the time it takes to simulate these large circuits. ”
Synopsys publishes DSO.ai tools that can be used to design analog circuits that scale the design with each new node.
"If you take a PLL or any other type of analog circuit, migrate from 7nm to 5nm or 5nm to 3nm, the process of migrating circuits from one node to another without changing the circuit is mature for the application of automation and artificial intelligence." So this is another area where we apply AI to accelerate this process and greatly reduce the effort and time required to migrate analog circuits. Synopsys executives explained.
According to Synopsys, similar AI capabilities could simplify the task of transferring chip designs between different foundries or process nodes. However, it is worth considering that the power, performance, and area characteristics (PPAc) of complex designs are customized for specific nodes. It is still uncertain whether AI can effectively migrate such designs from one foundry to another while retaining all the key features.
Synopsys has been providing DSO.ai platform for several years now, and so far, about 170 chips designed using this EDA tool have been completed. "We finished designing 100 chips in January and are now close to 170, and the adoption of this AI-based physical design in the customer base is really fast," Krishnamoorthy said. ”
6. TSO.ai help reduce test costs and time, and reduce test chip mode by more than 20%
After the chip is implemented and produced, the chip designer needs to verify that everything is working correctly, a process somewhat similar to IP verification. The chip is inserted into the tester device and a specific test pattern is run to confirm that the chip is functioning properly. Therefore, the number of patterns required to test an SoC (system-on-chip) or a real system is a major concern for product engineering.
▲TSO.ai function (Source: AnandTech)
Synopsys TSO.ai tool is designed to help semiconductor companies generate the right test patterns, reduce the number of patterns they must run by 20 to 30 percent, and speed up the silicon test/verification phase, then test all mass-produced chips with the same test sequence to ensure they function properly. The duration of the testing phase has a direct impact on costs, so it is particularly critical, especially for high-volume parts.
The Synopsys executive said: "We have shown how AI can greatly reduce the total number of modes required to test chips, reducing test modes by 20 to 30 percent. This translates directly into test costs and tester time, which is a big deal for Synopsys. ”
Artificial intelligence design chips can reduce engineering costs and computing costs
The use of AI in chip design can accelerate their time to market and significantly reduce development and production costs. According to Synopsys, hardware development costs for complex chips now reach $325 million (5nm) to $900 million (3nm), and depending on the design, the company is looking for ways to reduce costs by 30%-40%.
Typically, engineering costs account for about 60 percent of chip design costs and computing costs about 40 percent, and AI can be used to reduce both costs, according to Synopsys.
Krishnamoorthy said that when an established company designs a new chip, it includes 30 to 40 percent of new IP and 60 to 70 percent of mature IP. Traditionally, many engineers will migrate 60%-70% of IP from the previous node to the next node after minor modifications. However, this is an inefficient use of resources. By leveraging AI to apply previous learnings to the next generation, the time and resources required to complete these incremental blocks can be greatly reduced, allowing human engineers to speed up the process.
When it comes to new IP, it can be challenging and uncertain for engineers to determine the best way to architect and implement, and typically at least one engineer is required per IP block. This approach affects the number of people required for the project. However, leveraging AI as an assistant can help engineers quickly explore and learn new designs and architectures to determine the best strategy for implementation, validation, and testing. This can greatly reduce the investment required for new IP modules.
Wider deployment of DSO.ai, VSO.ai, and TSO.ai can reduce chip design computational costs by enabling smarter operation of EDA tools. Instead of relying on trial-and-error and random simulations of various circuits, these companies can reduce computational costs by using targeted AI operations to achieve similar results.
Synopsys offloads some of the chip design to AI-enabled EDA tools, which can greatly reduce the burden on engineering teams, freeing them up time and energy to develop new features, enhance product differentiation, or design more chips.
The company revealed that top chip design companies are already using Synopsys.ai, although not all chips are currently designed with the assistance of artificial intelligence. Synapsys.ai software suites mostly rely on CPU-accelerated AI, and while options like large circuit simulations can use GPU acceleration, most workloads run on Intel CPUs.
Conclusion: Synopsys develops new EDA tools to improve chip design efficiency and reduce costs
Synopsys develops Synopsys.ai that cover all phases of chip design.
Machine learning and reinforcement learning can be used in time-consuming and iterative design phases such as design space exploration, validation coverage, regression analysis, and test program generation, promising to reduce design costs, reduce production costs, increase yield, improve performance, and shorten time to market. Synopsys tools are useful for chips that will be manufactured in advanced processes such as 5nm, 3nm, and 2nm classes.
Source: AnandTech
![Academician Li Guojie: Let chip learning replace chip design and promote the full automation of EDA[fig]](data:image/gif;base64,R0lGODlhAQABAIAAAP///wAAACwAAAAAAQABAAACAkQBADs=)