HBM3 memory standard announced: the use of multi-layer stacking to introduce on-chip ECC error correction function

SK Hynix previously pioneered the HBM3 high-bandwidth memory chip, which uses multi-layer stacking, with a single chip capacity of up to 24 GB and a maximum bandwidth of 896GB/s. Now, the HBM3 memory standard has also been announced, compared to HBM2 memory, HBM3 bandwidth has doubled, the number of independent channels has reached 16, and each chip supports 32 channels. In addition, the chip can be stacked with 4 layers, 9 layers, and 12 layers, and the capacity of each layer of chips is optional from 8GB to 32GB (1GB to 4GB), and the first generation of products is expected to be 16GB single layer, which can be expanded to 16 layers in the future, and the single-chip capacity can reach 64GB. In addition, HBM3 also introduces an on-chip ECC error correction function.

In terms of power supply, the HBM3 chip adopts two operating voltages of 0.4V and 1.1V to improve energy efficiency. HBM3 will allow computers to reach higher performance caps while consuming less energy.

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