一天一道Verilog程式設計題（四）

題目如圖所示，話不多說直接上代碼。

module filter_data_store(
	input clk,
	input rst_b,
	input req_in,
	output req_in_ack,
	input [31:0]data_in,
	output reg data_out_vld,
	output reg [31:0] data_out
	);
	
	reg [31:0] data_reg;//輸入寄存器
	reg [2:0] ptr_w,ptr_r; //FIFO指針
	reg flag;              //輸入資料開始寄存信号
	wire full,empty;       //空滿标志
	parameter SP=32'h1b9_0000;
	
	//将資料輸入寄存器
	always @ (posedge clk or posedge rst_b)
	begin
		if (rst_b)
			data_reg<=0;
		else if ((req_in&&req_in_ack)==1'b1)
			data_reg<=data_in;
		else 
			data_reg<=data_reg;
	end
	
	//識别特殊資料，flag信号拉高
	always @ (posedge clk or posedge rst_b)
	begin
		if (rst_b)
			flag=1'b0;
		else if (data_reg==SP)
			flag=1'b1;
	end
	
	//寫指針
	always @ (posedge clk or posedge rst_b)
	begin	
		if (rst_b)
			ptr_w<=3'b000;
		else if (flag&&(!full))
			ptr_w<=ptr_w+1'b1;
	end
	
	//讀指針
	always @ (posedge clk or posedge rst_b)
	begin
		if (rst_b)
			ptr_r<=3'b000;
		else if (!empty)
			ptr_r<=ptr_r+1'b1;
	end
	//産生空滿标志
	assign full=({~ptr_w[2],ptr_w[1:0]}==ptr_r)?1'b1:1'b0;
	assign empty=(ptr_r==ptr_w)?1'b1:1'b0;
	assign req_in_ack=~full;  //FIFO滿時停止寫入
	
	reg [31:0]RAM[3:0];
	
	//資料存入FIFO
	always @ (posedge clk )
		if (flag&&(!full))
			RAM[ptr_w[1:0]]<=data_reg;
	
	//資料寫出，并殘生輸出标志
	always @ (posedge clk)
	begin
		if (!empty) begin
			data_out<=RAM[ptr_r[1:0]];
			data_out_vld<=1'b1;
		end
		else begin
			data_out<=32'h0;
			data_out_vld<=1'b0;
	    end
	end
endmodule 
	
           

測試子產品：`

```c
module filter_data_store_t();
	reg clk,rst_b;
	reg req_in;
	reg [31:0] data_in;
	wire [31:0] data_out;
	wire req_in_ack;
	wire data_out_vld;
	
	filter_data_store U1(.clk(clk),.rst_b(rst_b),
						 .req_in(req_in),.data_in(data_in),
						 .data_out(data_out),.req_in_ack(req_in_ack),
						 .data_out_vld(data_out_vld));
						 
	initial begin
		clk=1'b0;
		forever #10 clk=~clk;
	end
	
	initial begin
		req_in=1'b0;rst_b=1'b0;data_in=32'h1b8_fffd;
		#3 req_in=1'b1;rst_b=1'b1;
		#3 rst_b=1'b0;
	end
	
	always @(posedge clk)
	begin
		data_in<=data_in+1'b1;
	end
endmodule 
           

仿真結果如圖：