Xilinx的FPGA在使用DCM時的問題解決方案

在使用Xilinx的FPGA開發闆時，在設計時内部需要使用不同的時鐘頻率，可能會需要一個甚至多個DCM把所需要的時鐘頻率倍頻或者是分頻出來，在編譯、綜合、映射、布局布線的過程中會出現下列問題（ERROR）： 

ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM 

   site pair.  The clock component <u1/u0/DCM_SP_INST> is placed at site <DCM_X0Y1>.  The clock IO/DCM site can be 

   paired if they are placed/locked in the same quadrant.  The IO component <clk> is placed at site <P32>.  This will 

   not allow the use of the fast path between the IO and the Clock buffer. If this sub optimal condition is acceptable 

   for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a 

   WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to 

   very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the 

   COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to    override this clock rule. 

   < NET "clk" CLOCK_DEDICATED_ROUTE = FALSE; > 

   < PIN "u1/u0/DCM_SP_INST.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; >  

在UCF裡加入上面兩句的話，clk和clkin走的不是全局時鐘線： < NET "clk" CLOCK_DEDICATED_ROUTE = FALSE; > < 

PIN "u1/u0/DCM_SP_INST.CLKIN" CLOCK_DEDICATED_ROUTE = 

FALSE; >