Verilog實作加法器 行波進位（ripple carry）加法器，超前進位加法器

行波進位（ripple carry）加法器，将單個一比特全加器相連接配接，輸出加法和以及進位

首先先寫好單比特全加器的子產品

module full_adder(
		input a,
		input b,
		input c_in,
		output sum,
		output c_out);
		
	assign {c_out,sum} = a + b + c_in;
	
endmodule	
           

在行波進位加法器實作中，将N個全加器相連來實作N位數加法

module ripple_carry_adder(
		input [3:0] a,
		input [3:0] b,
		input c_in,
		output [3:0] sum,
		output c_out);
	
	wire sum1,sum2,sum3,sum4;
	wire c_out1,c_out2,c_out3;
	
	assign sum = {sum4,sum3,sum2,sum1};
	
	full_adder m0(
		.a(a[0]),
		.b(b[0]),
		.c_in(c_in),
		.sum(sum1),
		.c_out(c_out1));
		
	full_adder m1(
		.a(a[1]),
		.b(b[1]),
		.c_in(c_out1),
		.sum(sum2),
		.c_out(c_out2));
		
	full_adder m2(
		.a(a[2]),
		.b(b[2]),
		.c_in(c_out2),
		.sum(sum3),
		.c_out(c_out3));
		
	full_adder m3(
		.a(a[3]),
		.b(b[3]),
		.c_in(c_out3),
		.sum(sum4),
		.c_out(c_out));
	
endmodule
           

行波進位加法器testbench

module sim_ripple_carry_adder;

    reg [3:0] a;
    reg [3:0] b;
    reg c_in;
    wire [3:0] sum;
    wire c_out;
    
    ripple_carry_adder m (
		.a(a),
		.b(b),
		.c_in(c_in),
		.sum(sum),
		.c_out(c_out));
		
	initial
	   begin
	       a = 4'b1011;
	       b = 4'b1111;
	       c_in = 1'b0;
	   end

endmodule
           

功能仿真結果

RTL結構

超前進位加法器

module carry_lookahead_adder(
			input [3:0] a,
			input [3:0] b,
			input c_in,
			output [3:0] sum,
			output c_out);
			
		wire [3:0] G;
		wire [3:0] P;
		
        assign G = a&b;
        assign P = a^b;
        
		wire [4:0] c;
		assign c[0] = c_in;
		assign c[1] = G[0]|(P[0]&c_in);
		assign c[2] = G[1]|(P[1]&G[0])|(P[1]&P[0]&c_in);
		assign c[3] = G[2]|(P[2]&G[1])|(P[2]&P[1]&G[0])|(P[2]&P[1]&P[0]&c_in);
		assign c[4] = G[3]|(P[3]&G[2])|(P[3]&P[2]&G[1])|(P[3]&P[2]&P[1]&G[0])|(P[3]&P[2]&P[1]&P[0]&c_in);
		
		
		assign sum = a^b^c[3:0];
		assign c_out = c[4];
		
endmodule

           

testbench

`timescale 1ns / 1ps

module sim_carry_lookahead_adder;

        reg [3:0] a;
        reg [3:0] b;
        reg c_in;
        wire [3:0] sum;
        wire c_out;

          carry_lookahead_adder m0(
			.a(a),
			.b(b),
			.c_in(c_in),
			.sum(sum),
			.c_out(c_out));
			
		initial
		  begin
		      a = 4'b1001;
		      b = 4'b1111;
		      c_in = 1'b1;
		  end
endmodule