e.g.
導出網表
write_edif -security_mode all -force ./openrisc.edf
write_verilog -mode synth_stub -force ./openrisc_top.v
導出filelist
report_compile_order -file ./f.f
參考：
ug912 Vivado Design Suite Properties Reference Guide
ug835 Vivado Design Suite Tcl Command Reference Guide
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Tcl在Vivado中的應用
https://forums.xilinx.com/t5/Vivado/Vivado%E4%BD%BF%E7%94%A8%E8%AF%AF%E5%8C%BA%E4%B8%8E%E8%BF%9B%E9%98%B6-Tcl%E5%9C%A8Vivado%E4%B8%AD%E7%9A%84%E5%BA%94%E7%94%A8/td-p/525003
用Tcl定制Vivado設計實作流程
https://forums.xilinx.com/t5/Vivado/Vivado%E4%BD%BF%E7%94%A8%E8%AF%AF%E5%8C%BA%E4%B8%8E%E8%BF%9B%E9%98%B6-%E7%94%A8Tcl%E5%AE%9A%E5%88%B6Vivado%E8%AE%BE%E8%AE%A1%E5%AE%9E%E7%8E%B0%E6%B5%81%E7%A8%8B/td-p/546725