開源EDA工具

1.來自kakuyou

http://www.icarus.com/eda/verilog/

開源的verilog 編譯器，包含模拟器和基本邏輯綜合子產品。

http://www.geocities.com/SiliconValley/Campus/3216/GTKWave/gtkwave-win32.html

windows版的gtk-wave，一個圖形波形察看工具

http://embedded.eecs.berkeley.edu/research.htm

大名鼎鼎的伯克裡電子設計部，業界巨頭們的工具大部分都是建立在這個部

釋出的各種工具的基礎上。

2.來自Tony Hsu’s Technical View

原文：http://icguy.blogspot.com/2008/05/vmm.html

正當大家把注意力集中在新秀OVM身上、還在擔心非開源的VMM如何應對挑戰時，昨天Synopsys不聲不響地推出了VMM方法學的标準庫以及應用的源代碼。類似于OVM的官方網站OVM World(http://www.ovmworld.org/)，同時釋出的還有VMM開源網站http://www.vmmcentral.org/，VMM完整的實作都可以在該網站下載下傳。

Synopsys提供的代碼包括以下：

– VMM Standard Library

– VMM Register Abstraction Layer application

– VMM Reusable Environment Composition application

– VMM Memory Allocation Manager application

– VMM Hardware Abstraction Layer application

– VMM Data Stream Scoreboard application

– VMM Macro Library

這是個令人興奮的消息！随着驗證在IC設計中的重要性不斷被重視，EDA們巨頭們不斷推出新的政策吸引潛在客戶。從AVM開源到OVM開源再到 VMM的開源，我們看到的是一系列積極的舉措，在不斷地推進行業向前發展。不管怎麼樣，對客戶而言，終歸是好消息，你需要的是在選擇使用哪種方法進行驗證 工作學時停頓片刻，花點時間仔細考慮下。

既然VMM都接招了，OVM趕快行動吧！至少，也該把OVM的User Guide發出來給支援者一些“新鮮”吧！^_^

3.來自phixcoco

原文：http://blog.csdn.net/phixcoco/archive/2006/08/13/1057134.aspx

SourceForge上搜到的關于Verilog/SystemVerilog/SystemC的開源項目

A: Verilog相關：

·Eclipse Verilog editor

http://sourceforge.net/projects/veditor

http://icarus.com/eda/verilog/

Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.

·Icarus Verilog

http://sourceforge.net/projects/iverilog

Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2001 plus extensions.

·Source Navigator for Verilog

http://sourceforge.net/projects/snverilog

http://sources.redhat.com/sourcenav

Source Navigator for Verilog is a verilog parser that allows Source Navigator to be used with the Verilog Hardware Deion Language.

·Icarus Verilog Test Suite

http://sourceforge.net/projects/ivtest

Provides a GPL’d test suite for verification of the verilog language. This project is affiliated with the Icarus Verilog compiler effort at icarus.com.

·Vtracer

http://sourceforge.net/projects/vtracer

VTracer is a Verilog Testbench developer aid. Contains well documented Verilog-Perl co-simulation environment (TCP sockets based), structural Verilog parser, demo Testbenches.

·VeriWell Verilog Simulator

http://sourceforge.net/projects/veriwell

VeriWell is a full Verilog simulator. It supports nearly all of the IEEE1364-1995 standard, as well as PLI 1.0. Yes, VeriWell is the same simulator that was sold by Wellspring Solutions in the mid-1990 and was included with the Thomas and Moorby book

·PVSim Verilog Simulator

http://sourceforge.net/projects/pvsim

PVSim is a Verilog Simulator for Mac OS X that uses AlphaX editor’s Verilog mode and features a fast compile-simulate-display cycle.

·Verilog Construction Toolkit

http://sourceforge.net/projects/vct

The Verilog Construction Toolkit is a C++ library which provides the ability to read in, create and or modify verilog cell-based structural netlists.

·Verilog Netlist Viewer / Editor

http://sourceforge.net/projects/netedit

The purpose of this tool is creation of tcl/tk - based environment for convenient Verilog netlist viewing and editing. This tool will allow development of TCL s in order to make structural changes in verilog netlist.

·SystemC to Verilog RTL converter

http://sourceforge.net/projects/sysc2ver

sysc2ver - SystemC to Verilog RTL converter

·FPGA C Compiler

http://sourceforge.net/projects/fpgac

FpgaC compiles a subset of the C language to net lists which can be imported into an FPGA vendors tool chains. C provides an excellent alternative to VHDL/Verilog for algorithmic expression of FPGA reconfigurable computing tasks. More info on Home Page.

·vIDE

http://sourceforge.net/projects/vlogide

vIDE is a cross-platform tool for writing and simulating Verilog models. It provides user friendly project management and file editing, integrated simulation engine, waveform viewer, pre-compiled modules, and many other cool features.

·Covered

http://sourceforge.net/projects/covered

Covered is a Verilog code-coverage utility using VCD/LXT style dumpfiles and the design to generate line, toggle, combinational logic and FSM state/arc coverage reports. Covered also contains a built-in race condition checker and GUI report viewer.

·veri-indent

http://sourceforge.net/projects/veriindent

Veri-indent is a verilog source code Parser,Analyzer and Beautifier. (similar to c ‘indent’ , but more than that). Verilog source can be formatted and Symbol table, list of registers,wires,pli calls in source code can be extracted.

·Teal

http://sourceforge.net/projects/teal

TEAL - C++ multithreaded library to verfiy verilog designs

·Reed-Solomon Core Compiler

http://sourceforge.net/projects/rstk

RSTK is a C language program that generates Reed-Solomon HDL source code modules that can be compiled and synthesized using standard VHDL or Verilog compilers and synthesis tools.

·XSpiceHDL

http://sourceforge.net/projects/xspicehdl

XSpiceHDL, a mixed-mode XSpice-Verilog HDL co-simulation environment incorporating GUI schematic capture, modified XSpice3f5 based engine and TCP inter-process communications via CodeModel and VPI DLL, written in C++ using the wxWindows API.

B: SystemVerilog相關：(真是少得可憐)

·HDLObf

http://sourceforge.net/projects/hdlobf

HDLObf is intended to be a HDL Obfuscator and identifier name change utility. Primarily designed for Verilog/SystemVerilog. Support will be added for VHDL/SystemC in future.

C: SystemC相關：

·Open SystemC Initiative (OSCI)

http://sourceforge.net/projects/systemc

The Open SystemC Initiative (OSCI) is a collaborative effort to support and advance SystemC as a de facto standard for system-level design. SystemC is an interoperable, C++ SoC/IP modeling platform for fast system-level design and verification

·FERMAT SystemC Parser

http://sourceforge.net/projects/systemcxml

FERMAT’s SystemC Parser using Doxygen and Xerces-C++ XML

·SCLive

http://sourceforge.net/projects/sclive

SCLive is a modular Linux-Live Distribution dedicated to the OSCI SystemC simulator and it’s associated libraries. The distribution provides a fully working environement including a simulator kernel, wavefom viewer, IDE, tutorials and more.

·GreenSocs

http://sourceforge.net/projects/greensocs

http://www.greensocs.com

To develop SystemC infrustructure, basic IP, patches and add on library code for eventual standerdization. The GreenSocs project is made up of a number of contributions (sub projects). Please visit www.greensocs.com for more information.

www.opencores.org是IC行業有名的開源網站，有空了再到那裡去轉轉，說不定會有不少收獲！

4.來自sprhawk

原文：http://blog.chinaunix.net/u2/68344/article_85158.html

gEDA是一個Unix/Linux下作電路設計的軟體集合－－而非一個獨立的程式

官方網站見：http://www.geda.seul.org/

取自：http://www.geda.seul.org/tools/index.html

gEDA/gaf軟體包所帶的工具 (gschem and friends):

gschem :原理圖設計

gnetlist :網絡表生成

gattrib :屬性編輯器

symbols :符号庫

utils :工具集

gsymcheck :符号檢查

examples : 例子

docu……

開放的源代碼( opencores)網址（VHDL 和 VERILOG) [很好的設計參考]

http://www.opencores.org/cvsweb.shtml/ 有許多有用的源代碼，并且調試過

http://www.asics.ws/

http://www.oanda.com/convert/classic?user=freeipcore&lang=en

http://www.ssipex.com （收費的

http://www.altera.com.cn/support/examples/exm-index.html 設計範例

http://www.alse-fr.com/English/ips.html

http://www.soccentral.com/

http://www.eda.org/ 國際官方組織 (可以找到很多有用的東西

www.xilinx-china.com

www.aldec.com