armv8 mmu Memory region attributes

D5.5 Memory region attributes

記憶體屬性：記憶體類型，cache，shareability,記憶體一緻性等。

The memory region attribute fields control the memory type, accesses to the caches, and whether the memory region is Shareable and therefore is coherent. This section also describes some additional translation table fields, that this manual groups with the memory region attributes.

D5.5.1 The stage 1 memory region attributes

The description of the memory region attributes in a translation descriptor divides into:

Memory type and Cacheability

        These are described indirectly, by registers referenced by bits in the table descriptor. This is

        described as remapping the memory type and attribute description. Stage 1 memory region          type and  Cacheability attributes describes this encoding.

Shareability         The SH[1:0] field in the translation table descriptor encodes shareability  information. Stage 1  

          Shareability attribute, for Normal memory on page D5-2629 describes this encoding

Stage 1 memory region type and Cacheability attributes

頁表項中的AttrIndx[2:0]用來索引MAIR_ELx寄存器中定義的記憶體屬性

In the VMSAv8-64 translation table format, the AttrIndx[2:0] field in a block or page translation table descriptor  for a stage 1 translation indicates the 8-bit field in the MAIR_ELx that specifies the attributes for the corresponding  memory region. The required field is Attrn, where n = AttrIndx[2:0]. For more information about AttrIndx[2:0] see  Attribute fields in stage 1 VMSAv8-64 Block and Page descriptors on page D5-2601

記憶體類型：device或normal

Each MAIR_ELx.Attrn field defines, for the corresponding memory region:

• The memory type, Device or Normal.

• For Device memory, the Device memory type, one of:

— Device-nGnRnE.

— Device-nGnRE.

— Device-nGRE.

— Device-GRE.

• For Normal memory:

— The inner and outer cacheability, Non-cacheable, Write-Through, or Write-Back.

— For Write-Through Cacheable and Write-Back Cacheable regions, the Read-Allocate and

Write-Allocate policy hints, each of which is Allocate or No Allocate, and the Transient allocation

hints, if supported.

For more information about the memory type and attributes, see Memory types and attributes on page B2-153 and

Cacheability, cache allocation hints, and cache transient hints on page D4-2502

Stage 1 Shareability attribute, for Normal memory

講述頁表項中SH字段

When using the VMSAv8-64 translation table format, the SH[1:0] field in a block or page translation table descriptor specifies the Shareability attributes of the corresponding memory region. Table D5-35 shows the encoding of this field.

使用連續的頁表項組成一個連續的位址

D5.5.6 Other fields in the VMSAv8-64 translation table format descriptors

The following subsections describe the other fields in the translation table block and page descriptors:

• The Contiguous bit.

• IGNORED fields on page D5-2634.

• Field reserved for software use on page D5-2634.

The Contiguous bit

When the value of the Contiguous bit is 1, it indicates that the entry is one of a number of adjacent translation table entries that point to a contiguous output address range. The required number of adjacent entries depends on the current translation granule size, as follows:

16個相鄰的頁表項，可以祖冊一個contiguous輸出位址，但是這些頁表項必須通路權限和屬性一緻。

4KB granule  

    16 adjacent translation table entries point to a contiguous output address range that has the same permissions and attributes. These 16 entries must be aligned in the translation table. If accessing a full-sized 4KB translation table, this means that the top 5 of the 9 input addresses bits that index the descriptor positions in the translation table are the same for all of the entries. The contiguous output address range must be aligned to size of 16 translation table entries at the same translation table level.

......

IGNORED fields

忽略的字段，軟體可能用到

In the VMSAv8-64 translation table descriptors, the following fields are identified as IGNORED, meaning the

architecture guarantees that a PE makes no use of these fields:

• In the stage 1 and stage 2 Table descriptors, bits[58:51] and bits[11:2].

• In the stage 1 and stage 2 Block and Page descriptors, bit[63] and bits[58:55]. //bits[58:55]是留給軟體使用的，對于block或者page頁表項，軟體可以使用

• In the stage 1 and stage 2 Block and Page descriptors in an implementation that does not include

ARMv8.2-TTPBHA, bits[62:59].

Of these fields:

• In the stage 1 and stage 2 block and page descriptors, bits[58:55] are reserved for software use, see Field

reserved for software use.

• In the stage 2 block and page descriptors:

— Bit[63] is reserved for use by a System MMU.

— In an implementation that does not include ARMv8.2-TTPBHA, bits[62:59] are reserved for use by a System MMU.

Field reserved for software use

The architecture reserves a 4-bit IGNORED field in the Block and translation table descriptors, bits[58:55], for software use. The definition of IGNORED means the architecture guarantees that hardware makes no use of this field.