In semiconductor manufacturing, a process corner is an example of a design-of-experiments (DoE) technique that refers to a variation of fabrication parameters used in applying an integrated circuit design to a semiconductor wafer. Process corners represent the extremes of these parameter variations within which a circuit that has been etched onto the wafer must function correctly. A circuit running on devices fabricated at these process corners may run slower or faster than specified and at lower or higher temperatures and voltages, but if the circuit does not function at all at any of these process extremes, the design is considered to have inadequate design margin.[1]
To verify the robustness of an integrated circuit design, semiconductor manufacturers will fabricate corner lots, which are groups of wafers that have had process parameters adjusted according to these extremes, and will then test the devices made from these special wafers at varying increments of environmental conditions, such as voltage, clock frequency, and temperature, applied in combination (two or sometimes all three together) in a process called characterization. The results of these tests are plotted using a graphing technique known as a shmoo plot that indicates clearly the boundary limit beyond which a device begins to fail for a given combination of these environmental conditions.
Corner-lot analysis is most effective in digital electronics because of the direct effect of process variations on the speed of transistor switching during transitions from one logic state to another, which is not relevant for analog circuits, such as amplifiers.
Types of corners
When working in the schematic domain, we usually only work with front end of line (FEOL) process corners as these corners will affect the performance of devices. But there is an orthogonal set of process parameters that affect back end of line (BEOL) parasitics.
FEOL corners
One naming convention for process corners is to use two-letter designators, where the first letter refers to the N-channel MOSFET (NMOS) corner, and the second letter refers to the P channel (PMOS) corner. In this naming convention, three corners exist: typical, fast and slow. Fast and slow corners exhibit carrier mobilities that are higher and lower than normal, respectively. For example, a corner designated as FS denotes fast NFETs and slow PFETs.
There are therefore five possible corners: typical-typical (TT) (not really a corner of an n vs. p mobility graph, but called a corner, anyway), fast-fast (FF), slow-slow (SS), fast-slow (FS), and slow-fast (SF). The first three corners (TT, FF, SS) are called even corners, because both types of devices are affected evenly, and generally do not adversely affect the logical correctness of the circuit ==> with proper external conditions that is. The resulting devices can function at slower or faster clock frequencies, and are often binned as such. The last two corners (FS, SF) are called "skewed" corners, and are cause for concern. This is because one type of FET will switch much faster than the other, and this form of imbalanced switching can cause one edge of the output to have much less slew than the other edge. Latching devices may then record incorrect values in the logic chain.
==> "slew" : from TI
Slew rate is defined as the maximum rate of change of an op amps output voltage, and is given in units of volts per microsecond. Slew rate is measured by applying a large signal step, such as one volt, to the input of the op amp, and measuring the rate of change from 10% to 90% of the output signal's amplitude.
BEOL corners
In addition to the FETs themselves, there are more on-chip variation (OCV) effects that manifest themselves at smaller technology nodes (==> according to the linked video below, 90nm and below). These include process, voltage and temperature (PVT) variation effects on on-chip interconnect, as well as via structures.
Extraction tools often have a nominal corner to reflect the nominal cross section of the process target. Then the corners cbest and cworst (which were the only essential feature for older processes) were created to model the smallest and largest cross sections that are in the allowed process variation. A simple thought experiment shows that the smallest cross section with the largest vertical spacing will produce the smallest coupling capacitance. CMOS Digital circuits were more sensitive to capacitance than resistance so this variation was initially acceptable. As processes evolved and resistance of wiring became more critical, the additional rcbest and rcworst were created to model the minimum and maximum cross sectional areas for resistance. But the one change is that cross sectional resistance is not dependent on oxide thickness (vertical spacing between wires) so for rcbest the largest is used and for rcworst the smallest is used.
Recommended Readings
below are llinks to 2 rather well made short yet comprehensive summaries, including basic backgrounds for Process Corners and RC Corners:
You Don't Know About The Process Corners in VLSI Design ?
You Don't Know About The RC Corners in VLSI Design ?
Process Corners: Terminology and IntroductionIntroductionTerms and ElaborationComplexity of Process Corners in Advanced Nodes (< 7nm)
graph from Corner晶片TT,FF,SS_别想太多的部落格-CSDN部落格_tt ff ss
工藝角分析，corner analysis，一般有五種情況：
==> the the 2 letter are descriptions in the order of N-P(mos)
fast nmos and fast pmos （ff）
slow nmos and slow pmos （ss）
slow nmos and fast pmos （sf）
fast nmos and slow pmos （fs）
typical nmos and typical pmos （tt）
t,代表typical (平均值)
s,代表slow（電流小）
f,代表fast（電流大）
WCS (Worst Case Slow) : slow process, high temperature, lowest voltage
TYP (typical) : typical process, nominal temperature, nominal voltage
BCF (Best Case Fast ) : fast process, lowest temperature, high voltage
WCL (Worst Case @ Cold) : slow process, lowest temperature, lowest voltage
在進行功耗分析時，可能是另些組合如：
ML (Maximal Leakage ) : fast process, high temperature, high voltage
TL (typical Leakage ) : typical process, high temperature, nominal voltage
全局工藝差異(global_process_variations), 也稱為片間器件差異(inter-die device variations), 描述同一器件不同晶片間的差異。同一晶片的器件應用同一參數，器件的不同參數是互相獨立的，而且每個參數都是呈統計分布的。==> i.e. even though we set the process parameters, P, the same for a certain chip, the manufactured devices will inevitably display statistically regular variation due to manufacturing defects and techinical limitations.
Complexity of Process Corners in Advanced Nodes (< 7nm)
from Process Corner Explosion
"At 7nm and below, modeling what will actually show up in silicon is a lot more complicated."
“When the foundry refers to the timing goal, it means you need to hit the timing of the paths within 10% of, let’s say, the actual number,” Abadir said. “There is about 10% or 15% slack, depending on the maturity of the process, depending on things like how much yield they are hoping to get. In the final month or two of tapeout, the design team will start running the higher end corners that are very aggressive to see if these corners will take what they designed. They take the same design that they had, run the extraction against this worst case corner. They will also re-do the timing, re-do the power calculation, and see what happens to these numbers. If it’s way off, they start working on which ones are causing the problem and may tweak them. They try to do as much as they can in the last couple of months. It’s a matter of positioning and allowing a little bit of margin to see how far they are if the worst case conditions from the process variations happen, but it is a very non-scientific endeavor.”
Nevertheless, it’s also an essential endeavor. “We need to ensure our designs are manufacturable and demonstrate the required performance across manufacturing variability of advanced node processes,” said Sunil Bhardwaj
Advanced challenges for leading edge
Indeed, advanced nodes such as 7nm and below have made it that much more challenging to account for the corners in a design. “For interconnect corners, there was a large increase with the advent of multi-patterning,” Robertson said. “With multi-patterning, you know have geometries on the same layer represented in different masks, which means not only is there inter-layer variation (as has always been the case), but you know have intra-layer variation due to mask shifts. Anytime you introduce more processing steps or add layers there is an opportunity for variation that needs to be captured in a model or, potentially, in the description of another corner.”
