VIVADO debug 資源不夠

[Place 30-640] Place Check : This design requires more RAMB36/FIFO cells than are available in the target device. This design requires 145 of such cell types but only 140 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.

減小采樣深度，或者減少debug信号

debug ram占用是這樣計算的

所有debug信号的總位寬 x 采樣深度= 總bit數大小 ，再÷一個ram大小（36K bit）= 所占用的ram個數

所有debug信号的總位寬可以再set up debug 那裡看到