AXI4總線中BVALID與BREADY中的關系

AXI4總線突發式寫時序圖：

根據資料提供的時序圖誤認為BVALID信号在WLAST拉高後會立刻拉高一個時鐘周期，BREADY信号應該在AWVALID與AWREADY同時拉高後立即拉高，與BVALID信号同時拉低，是以用Verilog描述為(axi_bready即為BVALID信号)：

always @(posedge M_AXI_ACLK)

if(M_AXI_ARESETN == 0)

axi_bready <= 1’b0;

else if(M_AXI_BVALID==1’b1&&axi_bready==1’b1)

axi_bready <= 1’b0;

else if(axi_awvalid==1’b1&&M_AXI_AWREADY==1’b1)

axi_bready <= 1’b1;

但是通過ila抓取信号發現BVALID信号并不是在WLAST拉高後就立刻也拉高，是以上述寫法并不适用所有情況。後根據官方提供的例程，修改為：

always @(posedge M_AXI_ACLK)

begin

if (M_AXI_ARESETN == 0)

begin

axi_bready <= 1’b0;

end

// accept/acknowledge bresp with axi_bready by the master

// when M_AXI_BVALID is asserted by slave

else if (M_AXI_BVALID && ~axi_bready)

begin

axi_bready <= 1’b1;

end

// deassert after one clock cycle

else if (axi_bready)

begin

axi_bready <= 1’b0;

end

// retain the previous value

else

axi_bready <= axi_bready;

end

這種寫法才是最通用的方式。