AXI4总线中BVALID与BREADY中的关系

AXI4总线突发式写时序图：

根据资料提供的时序图误认为BVALID信号在WLAST拉高后会立刻拉高一个时钟周期，BREADY信号应该在AWVALID与AWREADY同时拉高后立即拉高，与BVALID信号同时拉低，所以用Verilog描述为(axi_bready即为BVALID信号)：

always @(posedge M_AXI_ACLK)

if(M_AXI_ARESETN == 0)

axi_bready <= 1’b0;

else if(M_AXI_BVALID==1’b1&&axi_bready==1’b1)

axi_bready <= 1’b0;

else if(axi_awvalid==1’b1&&M_AXI_AWREADY==1’b1)

axi_bready <= 1’b1;

但是通过ila抓取信号发现BVALID信号并不是在WLAST拉高后就立刻也拉高，所以上述写法并不适用所有情况。后根据官方提供的例程，修改为：

always @(posedge M_AXI_ACLK)

begin

if (M_AXI_ARESETN == 0)

begin

axi_bready <= 1’b0;

end

// accept/acknowledge bresp with axi_bready by the master

// when M_AXI_BVALID is asserted by slave

else if (M_AXI_BVALID && ~axi_bready)

begin

axi_bready <= 1’b1;

end

// deassert after one clock cycle

else if (axi_bready)

begin

axi_bready <= 1’b0;

end

// retain the previous value

else

axi_bready <= axi_bready;

end

这种写法才是最通用的方式。