讀 Linux 核心 MMU 筆記

PAE ( Physical address extension ) from Pentium Pro processor

• What is it?

  It is one kind of mechanism that translate 32-bit liner address to 36-bits physical address. In the near time when Intel was asked to increase the number of address pin connected address bus. With the close time, Page Size Extension(PSE-36) was introduced in the Pentium III processor.

• How to activated?

  Set the Physical address extension(PAE) flag in the cr4 control register. The Page Size(PS) flag in the page directory entry enables large page sizes (2 MB when PAE is enabled).

• What is different?

1. The 64 GB of RAM are split into 224 distinct page frames, and the physical address field of Page Table entries has been expanded from 20 to 24bits. Because a PAE Page Table entry must include the 12 flag bits and the 24 physical address bits, for a grand total of 36, the Page Table entry size had been doubled from 32 bits to 64 bits. As a result, a 4-KB PAE Page Table includes 512 entries instead of 1,024.
2. A new level of Page Table called the Page Directory Pointer Table (PDPT) consisting of four 64-bit entries had been introduced.
3. The cr3 control register contains a 27-bit Page Directory Pointer Table base address field. Because PDPTs are stored in the first 4 GB of RAM and aligned to a multiple of 32 bytes (25), 27 bits are sufficient to represent the base address of such tables.
4. When mapping liner addresses to 4KB pages (PS flag cleared in Page Directory entry), the 32 bits of a linear address are interpreted in the following way:

• cr3 : Points to a PDPT
• bits 31 - 30 : Point to 1of 4 possible entries in PDPT
• bits 29 - 21 : Point to 1 of 512 possible entries in Page Directory
• bits 20 - 12 : Point to 1 of 512 possible entries in Page Table
• bits 11 - 0 : Offset of 4-KB page

1. When mapping linear addresses to 2-MB pages ( PS flag set in Page Directory entry ), the 32 bits of a linear address are interpreted in the following way:

• cr3 : Points to a PDPT
• bits 31-30 : Point to 1 of 4 possible entries in PDPT
• bits 29-21 : Point to 1 of 512 possible entries in Page Directory
• bits 20-0 : offset of 2-MB page

Summary

To sumarize, once cr3 is set, it is possible to address up to 4 GB of RAM. If we want to address more RAM, we’ll have to put a new value in cr3 or change the content of the PDPT. However, the main problem with PAE is that linear addresses are still 32bits long. This forces kernel progrmmers to reuse the same linear addresses to map different areas of RAM. We’ll sketch how Linux initializes Page Tables when PAE is enabled in the later section, “Final kernel Page Table when RAM size is more than 4096 MB.” Clearly, PAE does not enlarge the liner address space of a process, because it deals only with physical addresses. Furthermore, only the kernel can modify the page tables of the processes, thus a process running in User Mode can’t use a physical address space larger than 4 GB. On the other hand, PAE allows the kernel to exploit up to 64 GB of RAM, and thus it increase significantly the number of processes in the system.