【FPGA,MPPT】基于FPGA的MPPT最大功率跟蹤系統verilog開發

1.軟體版本

MATLAB2019a,ISE14.7

2.本算法理論知識

MPPT，我們采用的是

FPGA的設計結構如下：

這裡，

第一，使用MATLAB模拟出光伏裝置PV輸出的電流和電壓資料，盡量貼近實際值

第二，緩沖器這裡，我考慮用RAM，雙口RAM，因為FIFO的話，沒法控制位址，隻能先入先出，RAM的話，我可以讀取存儲器裡面任意 為的資料，相當于更新版的FIFO。

3.部分源碼

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date:    02:59:07 06/05/2019 
// Design Name: 
// Module Name:    MPPT_module 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//
module MPPT_module(
                    i_clk,
              i_rst,
              i_PV_current,
              i_PV_voltage,
              o_PV_power,
              o_PV_max,
              o_PV_current,
              o_PV_voltage,
              o_state
                   );

input i_clk;
input i_rst;
input signed[15:0]i_PV_current;
input signed[15:0]i_PV_voltage;
output signed[31:0]o_PV_power;
output signed[31:0]o_PV_max;
output signed[15:0]o_PV_current;
output signed[15:0]o_PV_voltage;
output [1:0]o_state;

//power
multi_core multi_core_u(
  .a(i_PV_current), // input [15 : 0] a
  .b(i_PV_voltage), // input [15 : 0] b
  .p(o_PV_power) // output [31 : 0] p
);


reg signed[31:0]r_PV_k1;
reg signed[31:0]o_PV_max;
always @(posedge i_clk or posedge i_rst)
begin
     if(i_rst)
    begin
     o_PV_max <= 32'd0;
    r_PV_k1  <= 32'd0;
    end
else begin
     r_PV_k1  <= o_PV_power;
     if(o_PV_power>o_PV_max)
     o_PV_max <= o_PV_power; 
     else
    o_PV_max <= o_PV_max; 
     end
end



wire signed[31:0]Uk;
wire signed[31:0]Pk;

assign Uk = i_PV_voltage;
assign Pk = o_PV_power;

reg signed[15:0]dU = 16'd1;
reg signed[15:0]dU0= 16'd1;

reg signed[31:0]Pk1;
reg signed[15:0]Uk1;
reg signed[15:0]Uref;


//自适應步長的産生
reg[19:0]cnt;
always @(posedge i_clk or posedge i_rst)
begin
     if(i_rst)
    begin
    cnt  <= 20'd0;
    end
else begin
     if(cnt>=20'd35000)
     cnt <= 20'd35000;   
    else
    cnt <= cnt+20'd1;
     end
end


reg[1:0]o_state;
always @(posedge i_clk or posedge i_rst)
begin
     if(i_rst)
    begin
    Pk1      <= 32'd0; 
    Uk1      <= 16'd0;   
    
    Uref     <= 16'd0;

     o_state  <= 2'd0;     
    end
else begin

    Pk1      <= Pk;
    Uk1      <= Uk;
    
    
 
        if(Pk>=Pk1 & Uk>Uk1)  
        begin
        Uref    <= Uref + {dU0[15],dU0[15],dU0[15],dU0[15],dU0[15],dU0[15],dU0[15:6]};
        o_state <= 2'd0; 
        end
        if(Pk>=Pk1 & Uk<=Uk1)  
        begin
        Uref    <= Uref - {dU0[15],dU0[15],dU0[15],dU0[15],dU0[15],dU0[15],dU0[15:6]};
        o_state <= 2'd1; 
        end
        
        
        if(Pk<Pk1 & Uk>Uk1)  
        begin
        Uref <= Uref - {dU0[15],dU0[15],dU0[15],dU0[15],dU0[15],dU0[15],dU0[15:6]};
        o_state <= 2'd2; 
        end  
        
        if(Pk<Pk1 & Uk<=Uk1)  
        begin
        Uref <= Uref + {dU0[15],dU0[15],dU0[15],dU0[15],dU0[15],dU0[15],dU0[15:6]};
        o_state <= 2'd3; 
        end
    
     end
end
assign o_PV_voltage=Uref;
assign o_PV_current=dU0 ;



reg signed[31:0]Power_diffe;
reg signed[7:0] Current_diff;
always @(posedge i_clk or posedge i_rst)
begin
     if(i_rst)
    begin
    dU           <= 16'd1;
    dU0          <= 16'd1;   
     Power_diffe  <= 32'd0;
    Current_diff <= 8'd0;
     
    end
else begin


     Power_diffe  <= o_PV_max-r_PV_k1;
    Current_diff <= i_PV_current[15:8];

     
     if(cnt<20'd4000)
    begin
          if({Power_diffe[31-4:16-4],4'd0}>16'd10)
          dU0<= {16'd16};
      else
          dU0<= {Power_diffe[31-4:16-4],4'd0};
    end
     else begin
         dU0<= {Power_diffe[31-4:16-4],4'd0};
         end
 
 
 
     end
end

 

endmodule      

4.仿真分析

可以看到，最大功率pmax會跟蹤到每次峰值的最大值

對比MATLAB的仿真結果，就可以得到經典的MPPT性能名額圖了，如下所示：

5.參考文獻