1.實作偶數分頻
module div_even(clk,outclk,rst);//占空比為50%
input clk,rst;
output outclk;
reg outclk;
reg [3:0] count;
parameter N=4;//分頻系數 N=輸入時鐘頻率/輸出時鐘頻率
always @(posedge clk or posedge rst)
if(rst)
begin outclk<=1'b0;
count<=4'b0000;
end
else
begin
if(count == N/2-1)//第N/2-1個上升沿到來時outclk翻轉,計數器置零
begin outclk<=~outclk;
count<=4'b0000;
end
else
count<=count+1'b1;
end
endmodule
module test;
reg clk,rst;
wire outclk;
initial begin clk=1'b1;
rst=1'b1;
#40 rst=~rst;
end
always #10 clk=~clk;
div_even div_even(.clk(clk),.rst(rst),.outclk(outclk));
endmodule
二分頻電路圖：
四分頻隻需要複制電路就可以實作了！！
三分頻電路：
所示的譯碼複位電路，強制計數狀态傳回到初始全零狀态，就是用NOR（或非門）門電路把Q2，Q1=“11B”的狀态譯碼産生高電平複位脈沖，強迫FF1和FF2同時瞬間(在下一時鐘輸入Fi的脈沖到來之前)複零；
N=4 50%占空比
N=6 50%占空比
N=8 50%占空比
偶分頻實作任意占空比
module div_even(clk,outclk,rst);//4分頻25%占空比
input clk,rst;
output outclk;
reg outclk;
reg [3:0] count;//計數
parameter N=4;//分頻系數
always @(posedge clk or posedge rst)
if(rst)
begin outclk<=1'b1;
count<=4'b0000;
end
else
begin
if(count == 4'd0)//第1個上升沿到來時翻轉,計數器加1
begin outclk<=~outclk;
count<=count+1'b1;
end
else if(count == N-1)//第4個上升沿到來時outclk翻轉,計數器置零
begin
outclk<=~outclk;
count<=4'd0;
end
else//其他情況計數器加1
count<=count+1'b1;
end
endmodule
N=4 25%占空比
N=4 75%占空比
N=6 16.7%占空比
N=6 33%占空比
N=6 50%占空比
N=6 66%占空比
N=6 83%占空比
2.實作奇數分頻
module divodd_renyi(clk,outclk,rst);
input clk,rst;
output outclk;
reg outclk;
reg [3:0] count;//計數
parameter N=7;//分頻系數
always @(posedge clk or posedge rst)
if(rst)
begin outclk<=1'b0;
count<=4'b0000;
end
else
begin
if(count == 4'd2)//第0個上升沿到來時翻轉,計數器加1 4/7的占空比
begin
outclk<=~outclk;
count<=count+1'b1;
end
// else if(count == 2)//第4個上升沿到來時outclk翻轉,計數器置零
// begin
// outclk<=~outclk;
// count<=count+1'b1;
// end
else if(count == N-1)//第4個上升沿到來時outclk翻轉,計數器置零
begin
outclk<=~outclk;
count<=4'd0;
end
else//其他情況計數器加1
count<=count+1'b1;
end
endmodule
N=7 4/7占空比
N=7 5/7占空比
N=7 6/7占空比
N=7 3/7占空比
N=7 2/7占空比
N=7 1/7占空比
3.奇數分頻實作占空比為50%
module divodd50(clk,outclk,rst);
input clk;
input rst;
output outclk;
reg outclk1,outclk2;
reg [3:0] count1,count2;
parameter N=7;
always @(posedge clk or posedge rst)//上升沿觸發
begin
if(rst)
begin
count1 <= 4'd0;
outclk1 <= 1'b0;
end
else
begin
if(count1 == 4'd2)
begin
outclk1 <= ~outclk1;
count1 <= count1 + 1'b1;
end
else if(count1 == N-1)
begin
outclk1 <= ~outclk1;
count1 <= 4'd0;
end
else
begin
count1 <= count1 + 1'b1;
end
end
end
always @(negedge clk or posedge rst)//下降沿觸發
begin
if(rst)
begin
count2 <= 4'd0;
outclk2 <= 1'b0;
end
else
begin
if(count2 == 4'd2)
begin
outclk2 <= ~outclk2;
count2 <= count2 + 1'b1;
end
else if(count2 == N-1)
begin
outclk2 <= ~outclk2;
count2 <= 4'd0;
end
else
begin
count2 <= count2 + 1'b1;
end
end
end
assign outclk = outclk1 && outclk2;
endmodule
N=7 占空比50%