FPGA之VGA彩條測試代碼

FPGA之VGA測試代碼

功能：顯示彩條  （分辨率800*600）

module VGA(input CLOCK,RST,     //沒有DA轉換，也沒有專用的VGA轉換晶片

   output HSYNC,VSYNC,Red,Green,Blue//Red,Green,Blue是以最多顯示9種顔色

);

//-------------parameter-----------------/   800*600分辨率，

parameter Ha=8'd128,Hb=7'd88,Hc=10'd800,Hd=6'd40,He=11'd1056;

parameter Vo=3'd4,Vp=5'd23,Vq=10'd600,Vr=1'd1,Vs=10'd628;

//-------------module例化-----------------/

PLL U1(.inclk0(CLOCK),//晶振時鐘50MHz

.c0(CLK));   //經過PLL之後的時鐘40MHz

//---------------reg--------------------/

reg [10:0]CH;

reg [9:0]CV;

reg vsync;

reg hsync;

reg red,green,blue;

always @(posedge CLK, negedge RST)  // HSYNC信号控制

if(!RST)

begin CH<=10'd0; hsync<=1'b1; end 

else if(CH==He) begin CH<=10'd0; hsync<=1'b0;end 

  else if(CH>Ha)  begin hsync<=1'b1; CH<=CH+1'b1;end 

else begin  hsync<=1'b0; CH<=CH+1'b1; end 

always @(posedge CLK, negedge RST)  //VSYNC信号控制

if(!RST)

begin CV<=10'd0; vsync<=1'b1; end 

else 

begin  

if(CV==Vs) begin CV<=10'd0; vsync<=1'b0;end 

   else

  begin 

if(CV>Vo) begin  vsync<=1'b1; end 

else begin  vsync<=1'b0; end 

if(CH==He) begin CV<=CV+1'b1; end 

  end 

end   

always @(posedge CLK, negedge RST)  //VGA 顯示部分

if(!RST)

begin red<=1'b0; green<=1'b0; blue<=1'b0;end 

else begin 

if((CH>Ha+Hb)&&(CH<=Ha+Hb+7'd80))

begin red<=1'b1; green<=1'b0; blue<=1'b0;end

if((CH>Ha+Hb+7'd80)&&(CH<=Ha+Hb+8'd160))

begin red<=1'b0; green<=1'b0; blue<=1'b1;end

if((CH>Ha+Hb+8'd160)&&(CH<=Ha+Hb+9'd240))

begin red<=1'b1; green<=1'b1; blue<=1'b0;end

if((CH>Ha+Hb+9'd240)&&(CH<=Ha+Hb+9'd320))

begin red<=1'b1; green<=1'b0; blue<=1'b0;end

if((CH>Ha+Hb+9'd320)&&(CH<=Ha+Hb+9'd400))

begin red<=1'b0; green<=1'b1; blue<=1'b0;end

if((CH>Ha+Hb+9'd400)&&(CH<=Ha+Hb+9'd480))

begin red<=1'b1; green<=1'b1; blue<=1'b0;end

if((CH>Ha+Hb+9'd480)&&(CH<=Ha+Hb+10'd600))

begin red<=1'b0; green<=1'b1; blue<=1'b0;end

end 

assign Red=red;

assign Green = green;

assign Blue = blue;

assign HSYNC = hsync;

assign VSYNC = vsync;

endmodule