基于basys3開發闆的四位數位管掃描顯示的VHDL實作

基于Vivado的四位數位管掃描顯示VHDL實作

• 一、所需平台：
• 二、遇到的一些問題：
• 三、相關代碼：
• • 1、代碼
  • 2、testbench檔案：
  • 3、限制檔案xdc：
• 四、基于vhdl的仿真檔案書寫（testbench）
• 五、basys3開發闆限制（xdc）參考檔案：
• 六、上闆示範

最近在學習FPGA，記錄一下自己遇到的一些問題。

一、所需平台：

1、硬體平台：basys3（XILINX）；

2、開發軟體：vivado2017.4;

3、使用語言：VHDL；

二、遇到的一些問題：

1、位選信号掃描頻率大概在1000hz左右，顯示正常。頻率過高顯示亂碼，過低則會出現閃爍。（利用人眼暫留原理）

2、由1可知，我們要涉及到時鐘分頻。開發闆時鐘為100MHZ，是以分頻數N為100000，用計數器分頻時，計數個數為（m=N/2-1）,一定要給計數賦初值，否則無法計數，導緻沒有分頻。還有就是目标分頻時鐘clk_f也要賦初值。

3、數位管的位選及單個數位管的段選信号，一定要厘清楚是共陰還是共陽，及高電平/低電平有效。（basys3是共陽，低電平有效）

4、數位管的段控制信号的順序一定要和管腳限制相比對,八段數位管段由低到高位為（abcdefgh）。（h為小數點，有些沒有）

三、相關代碼：

1、代碼

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity scan_led is
    Port ( clk : in STD_LOGIC;
           seg : out STD_LOGIC_VECTOR (7 downto 0);         --段顯示控制信号
          scan : out STD_LOGIC_VECTOR (3 downto 0));         --數位管位址選擇控制信号
end scan_led;

architecture Behavioral of scan_led is
    signal cnt4 : integer range 0 to 3;
    signal data : integer range 0 to 15;
    signal cnt  : integer range 0 to 49999:=0;
    signal clk_f: std_logic:='0';    
begin
--時鐘分頻産生1000hz  
  clk_f_gen:process(clk)
  begin
    if(clk'event and clk='1')then
      cnt<=cnt+1;
      if(cnt=49999)then
        cnt<=0;
      end if;
    end if;
  end process;
  
  process(clk)
  begin
    if(clk'event and clk='1')then
      if(cnt=0)then
        clk_f<=not clk_f;
      end if;
    end if;
  end process;

 --用于掃描數位管位址的計數器
  process(clk)
  begin
    if(clk_f'event and clk_f='1')then
      cnt4<=cnt4+1;
      if(cnt4=3) then
        cnt4<=0;     
      end if;
    end if;
  end process;
  
--數位管位址掃描
  process(clk)
  begin
    if(clk'event and clk='1')then         
      case cnt4 is
        when 0 =>scan<="0111"; 
        when 1 =>scan<="1011"; 
        when 2 =>scan<="1101"; 
        when 3 =>scan<="1110"; 
        when others=>null;
      end case;
    end if;
  end process;

--四個數位管分别顯示的數字
  process(clk)
  begin
    if(clk'event and clk='1')then
      case cnt4 is
        when 0 =>data<=0;                     --顯示0223
        when 1 =>data<=2;
        when 2 =>data<=2;
        when 3 =>data<=3;
        when others=>null;
      end case; 
    end if;
  end process;
  
--七段譯碼
  process(clk)
  begin
   if(clk'event and clk='1')then
    case data is
      when 0  =>seg<="00000011";
      when 1  =>seg<="10011111";     
      when 2  =>seg<="00100101";
      when 3  =>seg<="00001101";
      when 4  =>seg<="10011001";
      when 5  =>seg<="01001001";
      when 6  =>seg<="01000001";
      when 7  =>seg<="00011111";
      when 8  =>seg<="00000001";
      when 9  =>seg<="00001001";
      when 10 =>seg<="00010001";
      when 11 =>seg<="11000001";
      when 12 =>seg<="01100011";
      when 13 =>seg<="10000101";
      when 14 =>seg<="01100001"; 
      when 15 =>seg<="01110001";
      when others=>null;    
    end case;
  end if;
  end process;
  

end Behavioral;

           

2、testbench檔案：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity scan_tb is
--  Port ( );
end scan_tb;

architecture Behavioral of scan_tb is
  component scan_led
    port(
         clk  : in  STD_LOGIC;
         seg  : out STD_LOGIC_VECTOR (7 downto 0);         
         scan : out STD_LOGIC_VECTOR (3 downto 0)
         );          
  end component;
--輸入信号
  signal clk  : STD_LOGIC := '0';
--輸出信号
  signal seg  : STD_LOGIC_VECTOR(7 downto 0);
  signal scan : STD_LOGIC_VECTOR(3 downto 0);
--時鐘周期的定義
  constant clk_period:time:=20ns;  
begin
  instant: scan_led port map
    (
      clk=>clk,seg=>seg,scan=>scan
    );    
  clk_gen:process
  begin
    clk<='1';
    wait for clk_period/2;
    clk<='0';
    wait for clk_period/2; 
  end process;  
end Behavioral;

           

3、限制檔案xdc：

set_property PACKAGE_PIN W5 [get_ports clk]                            
  set_property IOSTANDARD LVCMOS33 [get_ports clk]
  create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
  
set_property PACKAGE_PIN W7 [get_ports {seg[7]}]                    
  set_property IOSTANDARD LVCMOS33 [get_ports {seg[7]}]
set_property PACKAGE_PIN W6 [get_ports {seg[6]}]                    
  set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
set_property PACKAGE_PIN U8 [get_ports {seg[5]}]                    
  set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
set_property PACKAGE_PIN V8 [get_ports {seg[4]}]                    
  set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
set_property PACKAGE_PIN U5 [get_ports {seg[3]}]                    
  set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
set_property PACKAGE_PIN V5 [get_ports {seg[2]}]                    
  set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
set_property PACKAGE_PIN U7 [get_ports {seg[1]}]                    
  set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
set_property PACKAGE_PIN V7 [get_ports {seg[0]}]                            
  set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]

set_property PACKAGE_PIN U2 [get_ports {scan[0]}]                    
  set_property IOSTANDARD LVCMOS33 [get_ports {scan[0]}]
set_property PACKAGE_PIN U4 [get_ports {scan[1]}]                    
  set_property IOSTANDARD LVCMOS33 [get_ports {scan[1]}]
set_property PACKAGE_PIN V4 [get_ports {scan[2]}]                    
  set_property IOSTANDARD LVCMOS33 [get_ports {scan[2]}]
set_property PACKAGE_PIN W4 [get_ports {scan[3]}]                    
  set_property IOSTANDARD LVCMOS33 [get_ports {scan[3]}]
           

四、基于vhdl的仿真檔案書寫（testbench）

詳情參照下面部落格：連結: [link]（https://blog.csdn.net/chiyiwei7384/article/details/79753435）.

五、basys3開發闆限制（xdc）參考檔案：

## This file is a general .xdc for the Basys3 rev B board
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project

## Clock signal
#set_property PACKAGE_PIN W5 [get_ports clk]                            
    #set_property IOSTANDARD LVCMOS33 [get_ports clk]
    #create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
 
## Switches
#set_property PACKAGE_PIN V17 [get_ports {sw[0]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
#set_property PACKAGE_PIN V16 [get_ports {sw[1]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
#set_property PACKAGE_PIN W16 [get_ports {sw[2]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
#set_property PACKAGE_PIN W17 [get_ports {sw[3]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
#set_property PACKAGE_PIN W15 [get_ports {sw[4]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
#set_property PACKAGE_PIN V15 [get_ports {sw[5]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
#set_property PACKAGE_PIN W14 [get_ports {sw[6]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
#set_property PACKAGE_PIN W13 [get_ports {sw[7]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
#set_property PACKAGE_PIN V2 [get_ports {sw[8]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
#set_property PACKAGE_PIN T3 [get_ports {sw[9]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
#set_property PACKAGE_PIN T2 [get_ports {sw[10]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
#set_property PACKAGE_PIN R3 [get_ports {sw[11]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
#set_property PACKAGE_PIN W2 [get_ports {sw[12]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
#set_property PACKAGE_PIN U1 [get_ports {sw[13]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
#set_property PACKAGE_PIN T1 [get_ports {sw[14]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
#set_property PACKAGE_PIN R2 [get_ports {sw[15]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
 
## LEDs
#set_property PACKAGE_PIN U16 [get_ports {led[0]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
#set_property PACKAGE_PIN E19 [get_ports {led[1]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
#set_property PACKAGE_PIN U19 [get_ports {led[2]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
#set_property PACKAGE_PIN V19 [get_ports {led[3]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
#set_property PACKAGE_PIN W18 [get_ports {led[4]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
#set_property PACKAGE_PIN U15 [get_ports {led[5]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
#set_property PACKAGE_PIN U14 [get_ports {led[6]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
#set_property PACKAGE_PIN V14 [get_ports {led[7]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
#set_property PACKAGE_PIN V13 [get_ports {led[8]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
#set_property PACKAGE_PIN V3 [get_ports {led[9]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
#set_property PACKAGE_PIN W3 [get_ports {led[10]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
#set_property PACKAGE_PIN U3 [get_ports {led[11]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
#set_property PACKAGE_PIN P3 [get_ports {led[12]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
#set_property PACKAGE_PIN N3 [get_ports {led[13]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
#set_property PACKAGE_PIN P1 [get_ports {led[14]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
#set_property PACKAGE_PIN L1 [get_ports {led[15]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
       
##7 segment display
#set_property PACKAGE_PIN W7 [get_ports {seg[0]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
#set_property PACKAGE_PIN W6 [get_ports {seg[1]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
#set_property PACKAGE_PIN U8 [get_ports {seg[2]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
#set_property PACKAGE_PIN V8 [get_ports {seg[3]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
#set_property PACKAGE_PIN U5 [get_ports {seg[4]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
#set_property PACKAGE_PIN V5 [get_ports {seg[5]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
#set_property PACKAGE_PIN U7 [get_ports {seg[6]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]

#set_property PACKAGE_PIN V7 [get_ports dp]                            
    #set_property IOSTANDARD LVCMOS33 [get_ports dp]

#set_property PACKAGE_PIN U2 [get_ports {an[0]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
#set_property PACKAGE_PIN U4 [get_ports {an[1]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
#set_property PACKAGE_PIN V4 [get_ports {an[2]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
#set_property PACKAGE_PIN W4 [get_ports {an[3]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]

##Buttons
#set_property PACKAGE_PIN U18 [get_ports btnC]                        
    #set_property IOSTANDARD LVCMOS33 [get_ports btnC]
#set_property PACKAGE_PIN T18 [get_ports btnU]                        
    #set_property IOSTANDARD LVCMOS33 [get_ports btnU]
#set_property PACKAGE_PIN W19 [get_ports btnL]                        
    #set_property IOSTANDARD LVCMOS33 [get_ports btnL]
#set_property PACKAGE_PIN T17 [get_ports btnR]                        
    #set_property IOSTANDARD LVCMOS33 [get_ports btnR]
#set_property PACKAGE_PIN U17 [get_ports btnD]                        
    #set_property IOSTANDARD LVCMOS33 [get_ports btnD]
 
##Pmod Header JA
##Sch name = JA1
#set_property PACKAGE_PIN J1 [get_ports {JA[0]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}]
##Sch name = JA2
#set_property PACKAGE_PIN L2 [get_ports {JA[1]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}]
##Sch name = JA3
#set_property PACKAGE_PIN J2 [get_ports {JA[2]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}]
##Sch name = JA4
#set_property PACKAGE_PIN G2 [get_ports {JA[3]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}]
##Sch name = JA7
#set_property PACKAGE_PIN H1 [get_ports {JA[4]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}]
##Sch name = JA8
#set_property PACKAGE_PIN K2 [get_ports {JA[5]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}]
##Sch name = JA9
#set_property PACKAGE_PIN H2 [get_ports {JA[6]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}]
##Sch name = JA10
#set_property PACKAGE_PIN G3 [get_ports {JA[7]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}]

##Pmod Header JB
##Sch name = JB1
#set_property PACKAGE_PIN A14 [get_ports {JB[0]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}]
##Sch name = JB2
#set_property PACKAGE_PIN A16 [get_ports {JB[1]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}]
##Sch name = JB3
#set_property PACKAGE_PIN B15 [get_ports {JB[2]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}]
##Sch name = JB4
#set_property PACKAGE_PIN B16 [get_ports {JB[3]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}]
##Sch name = JB7
#set_property PACKAGE_PIN A15 [get_ports {JB[4]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}]
##Sch name = JB8
#set_property PACKAGE_PIN A17 [get_ports {JB[5]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}]
##Sch name = JB9
#set_property PACKAGE_PIN C15 [get_ports {JB[6]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}]
##Sch name = JB10 
#set_property PACKAGE_PIN C16 [get_ports {JB[7]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}]
 
##Pmod Header JC
##Sch name = JC1
#set_property PACKAGE_PIN K17 [get_ports {JC[0]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}]
##Sch name = JC2
#set_property PACKAGE_PIN M18 [get_ports {JC[1]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}]
##Sch name = JC3
#set_property PACKAGE_PIN N17 [get_ports {JC[2]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}]
##Sch name = JC4
#set_property PACKAGE_PIN P18 [get_ports {JC[3]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}]
##Sch name = JC7
#set_property PACKAGE_PIN L17 [get_ports {JC[4]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}]
##Sch name = JC8
#set_property PACKAGE_PIN M19 [get_ports {JC[5]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}]
##Sch name = JC9
#set_property PACKAGE_PIN P17 [get_ports {JC[6]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
##Sch name = JC10
#set_property PACKAGE_PIN R18 [get_ports {JC[7]}]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]

##Pmod Header JXADC
##Sch name = XA1_P
#set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}]
##Sch name = XA2_P
#set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
##Sch name = XA3_P
#set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
##Sch name = XA4_P
#set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
##Sch name = XA1_N
#set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
##Sch name = XA2_N
#set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
##Sch name = XA3_N
#set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
##Sch name = XA4_N
#set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]

##VGA Connector
#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
#set_property PACKAGE_PIN P19 [get_ports Hsync]                        
    #set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
#set_property PACKAGE_PIN R19 [get_ports Vsync]                        
    #set_property IOSTANDARD LVCMOS33 [get_ports Vsync]

##USB-RS232 Interface
#set_property PACKAGE_PIN B18 [get_ports RsRx]                        
    #set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
#set_property PACKAGE_PIN A18 [get_ports RsTx]                        
    #set_property IOSTANDARD LVCMOS33 [get_ports RsTx]

##USB HID (PS/2)
#set_property PACKAGE_PIN C17 [get_ports PS2Clk]                        
    #set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
    #set_property PULLUP true [get_ports PS2Clk]
#set_property PACKAGE_PIN B17 [get_ports PS2Data]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]    
    #set_property PULLUP true [get_ports PS2Data]

##Quad SPI Flash
##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
##STARTUPE2 primitive.
#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}]
#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}]
#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}]
#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}]
#set_property PACKAGE_PIN K19 [get_ports QspiCSn]                    
    #set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]
           

六、上闆示範

第一次寫部落格，沒什麼經驗，主要是記錄自己學習FPGA的過程及遇到的問題，希望對有需要的人有幫助，有什麼問題大家共同讨論。