laitimes

What is the LDO principle of a MOS transistor and how can it be prevented from reversing currents?

author:Micro Semiconductor

LDO low dropout linear regulators, traditional linear regulators have dropout voltages up to 2V, but LDOs are only a few hundred mV.

LDO is a negative feedback system: when Vout increases, the voltage on R2 increases, the amplifier output voltage increases, the PMOS VGS voltage decreases, and then the output current decreases and the output voltage decreases.

What is the LDO principle of a MOS transistor and how can it be prevented from reversing currents?

Let's compare NMOS and PMOS in LDOs.

What is the LDO principle of a MOS transistor and how can it be prevented from reversing currents?

The PMOS architecture of the LDO has a lower voltage drop at higher output voltages.

When VIN gets closer to Vout, the error amplifier will negatively increase the gate-source voltage Vgs, reduce RDS, and maintain a regulated voltage.

However, there is a case where at certain points the error amplifier output will reach a saturation state at the ground and cannot drive the Vgs to increase negatively.

What is the LDO principle of a MOS transistor and how can it be prevented from reversing currents?

In other words, as the input voltage increases, the Vgs increases negatively, and the voltage drop voltage decreases as the input voltage increases.

In the NDO architecture, the feedback loop still controls the RDS, but as the input voltage approaches the output voltage, the error amplifier increases the VGS and decreases the RDS, maintaining a regulated voltage.

What is the LDO principle of a MOS transistor and how can it be prevented from reversing currents?

Similarly, at a certain point, the VGS can no longer be raised, and the error amplifier output reaches saturation at the supply voltage VIN.

In this case, RDS is the minimum value, which is multiplied by the output current IOUT, which is the voltage drop voltage.

However, the error amplifier output reaches saturation at VIN, and as VIN approaches VOUT(nom), VGS decreases, preventing ultra-low voltage drops.

Generally, the NMOS LDO will use an auxiliary voltage rail, which is the bias voltage. It allows the LDO to maintain high Vgs and achieve ultra-low voltage dropout at low output voltages, sometimes without providing an auxiliary voltage rail, but can also achieve low voltage dropout at lower output voltages, which can be replaced by an internal charge pump.

Here's the question, what happens if there is a reverse current?

The current is originally flowing from the input voltage to the output voltage, but from the output voltage to the input voltage, and this current often passes through the body diode of the LDO and does not flow through the normal conductive channel, which may cause the temperature of the device to rise, electromigration or latch-up effect, and cause device damage.

Here are 3 ways to prevent it.

  1. Schottky diodes are used
What is the LDO principle of a MOS transistor and how can it be prevented from reversing currents?
  1. Diodes are used before LDOs
What is the LDO principle of a MOS transistor and how can it be prevented from reversing currents?

3. Add an additional FET

What is the LDO principle of a MOS transistor and how can it be prevented from reversing currents?

Partners who have other insights can leave a message in the comment area, and we will discuss the details later!

Well, that's all for this issue. Thanks for reading!

What is the LDO principle of a MOS transistor and how can it be prevented from reversing currents?
What is the LDO principle of a MOS transistor and how can it be prevented from reversing currents?
What is the LDO principle of a MOS transistor and how can it be prevented from reversing currents?

(Some of the above pictures and data come from the Internet)