本文由半导体产业纵横（ID：ICVIEWS）编译自technews
Strive for the advanced process market.
As Moore's Law evolves, transistors are getting smaller and denser, and the number of stacking layers is increasing, and it may take 10~20 layers of stacking to provide power and data signals to the transistors below, which causes the line layer where interconnects and power lines coexist into an increasingly chaotic network. At the same time, during the downward transmission of electrons, there will be an IR voltage drop, resulting in power loss.
In addition to the loss of power, the space occupied by the power supply lines is also a problem. How to solve the problem of crowding out the resources of the signal network and the power supply network, so that the components are miniaturized, has become the main challenge for chip designers, which causes the semiconductor industry to begin to transfer the power supply network to the back of the chip.
TSMC's super rail will be unveiled on the A16 process in 2025, and the technology is complex to improve chip efficiency
TSMC, a leading wafer foundry, recently announced at the North American Technology Forum that the A16 node process not only accommodates more transistors, improves computing efficiency, but also reduces energy consumption. More concerningly, the introduction of the A16 chip, which combines the Super PowerRail architecture with nanosheet transistors, will drive the development of faster and more efficient data center processors. In particular, TSMC A16 uses different chip wiring. The wires that deliver power to the transistors will be located below the transistors rather than above them, known as back-side power supply, which facilitates the production of more efficient chips.
In fact, one of the ways to optimize a processor is to mitigate the IR drop, which reduces the voltage received by the chip transistors, reducing performance. A16 wires are less prone to voltage drops, simplifying power distribution and allowing chip circuitry to be more tightly packed, with the goal of putting more transistors into the processor to increase computing power. Moreover, a transistor consists of four main elements, the source, the drain, the channel, and the gate. The source is the entry point where the current flows into the transistor, the draw is the outlet, and the channel and gate are responsible for coordinating the movement of electrons.
TSMC uses A16 process technology to directly connect the power transmission line to the source and the extraction electrode. In this regard, TSMC said that the decision to more complex design was made because it would help improve the efficiency of the chip. In this case, the A16 with Superrail will increase the computing speed by 8%~10% with the same Vdd (operating voltage) compared to N2P, or reduce the power consumption by 15%~20% and increase the chip density by up to 1.10 times with the same computing speed, supporting data center products.
Intel PowerVia will be production-ready on the Intel 20A in 2024
Like TSMC's Superrail, Intel has also launched PowerVia, a backside power solution. According to reports, the power cord may have occupied 20% of the space on the chip, but the PowerVia back power supply technology saves this space, which also means that the interconnection layer can become a little looser.
In this regard, the Intel team has also specially created the Blue Sky Creek test chip to prove that the power supply and interconnect wires of the back power supply technology can be separated and the wire diameter is larger to improve power supply and signal transmission. The test results show that the standard cell utilization rate in most areas of the chip is more than 90%, the platform voltage is reduced by 30%, and the frequency increase is 6%, while the cell density is also greatly increased, and the cost is expected to be reduced. The PowerVia test chip also exhibits good thermal characteristics, in line with the higher power density expected from logic scaling.
In addition, PowerVia is also planned to be introduced into Intel Foundry Services (IFS) to enable customers to design chips that can achieve faster improvements in product efficiency and performance. According to the official introduction of Intel's PowerVia backside power supply technology, Intel will use PowerVia backside power supply technology and RibbonFET full-surround gate transistor architecture on Intel's 20A process technology, and it is expected that production will be ready in the first half of 2024 for the future mass-produced client ARL platform, and the first stepping is being launched in the fab.
Samsung plans to start applying it to the SF1.4 process in 2027
As for Samsung, another competitor of TSMC, in addition to taking the lead in transforming GAA transistor technology, its backside power supply technology (BSPDN) is also Samsung's killer feature in chasing advanced manufacturing processes. According to previous South Korean media reports, Jung Ki-tae Jung, chief technology officer of Samsung's foundry department, has announced that the backside power supply technology will be used in the 1.4nm process in 2027.
The report pointed out that compared with the traditional front-end power supply network, Samsung's backside power supply network successfully reduced the consumption of wafer area by 14.8%, the chip has more space, can add more transistors, improve the overall performance, and reduce the wiring length by 9.2%, which helps to reduce the resistance so that more current can pass through, reduce power consumption, and improve power delivery. According to an official from Samsung Electronics, the mass production time of semiconductors using backside power supply technology may vary depending on the customer's schedule. Samsung is investigating customer demand for backside power supply technology applications.
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