TSMC III said a new chip-making technology called "A16" will go into production in the second half of 2026 against long-time rival Intel – who can make the world's fastest chip.
TSMC is the world's largest contract manufacturer of advanced computing chips and a major supplier to Nvidia and Apple, which made the announcement at a conference in Santa Clara, California, where TSMC executives said AI chipmakers could be the first adopters of the technology, rather than smartphone makers.
Analysts told Reuters that the technology announced on Wednesday could call into question Intel's claim in February that it would overtake TSMC to make the world's fastest computing chip with a new technology that Intel calls "14A."
Kevin Zhang, TSMC's senior vice president of business development, told reporters that the company is developing a new A16 chip manufacturing process faster than expected due to demand from AI chip companies, but did not name specific customers.
AI chip companies "really want to optimize their designs to get every ounce of performance that we have," Zhang said.
TSMC does not see the need for ASML's High NA EUV lithography machine to build A16 chips using ASML's High NA EUV lithography machine, Zhang said. Intel revealed last week that it plans to be the first to use the machines, which cost $373 million each, to develop its 14A chips.
TSMC also revealed a new technology that powers computer chips from the back of the chip, helping to speed up AI chips, which will be launched in 2026. Intel has already announced a similar technology that aims to be one of its main competitive advantages.
With TSMC's industry-leading N3E technology now in production and N2 also on track for production in the second half of 2025, TSMC has introduced the A16, the next technology on its roadmap, TSMC said. The A16 will combine TSMC's Super Power Rail architecture with its nanosheet transistors, with production scheduled for 2026. It improves logic density and performance by dedicating front-end cabling resources to the signal, making the A16 ideal for HPC products with complex signal routes and dense power delivery networks. Compared to TSMC's N2P process, the A16 will provide an 8-10% speed increase at the same Vdd (positive supply voltage), a 15-20% reduction in power consumption at the same speed, and a chip density increase of up to 1.10x for data center products.
Analysts said the announcements cast doubt on Intel's claim that it would regain the world's chip manufacturing crown.
Dan Hutcheson, vice president of analyst firm TechInsights, said of Intel, "It's controversial, but by some metrics, I don't think they're ahead of the curve. But Kevin Krewell, head of TIRIAS Research, warned that Intel and TSMC's technology is still years away from delivering the technology, and that the real chip needs to be proven to match its keynote.
TSMC's new technology was reportedly announced at a technical conference in North America, which is reportedly a third world conference held by the company in North America. According to related reports, the company also announced the following technologies at the meeting:
TSMC NanoFlex Nanosheet Transistor Innovations: TSMC's upcoming N2 technology, which will be launched alongside TSMC NanoFlex, is the company's next breakthrough in design technology co-optimization. TSMC NanoFlex provides designers with the flexibility of N2 standard cells, the basic building blocks of chip design, with short cells emphasizing small area and higher power efficiency, and tall cells maximizing performance. Customers are able to optimize the combination of short and high cells in the same design module, adapting their designs to achieve the best power, performance, and area trade-offs for their applications.
N4C Technology: TSMC announced the launch of N4C, which is an extension of N4P technology that reduces chip costs by up to 8.5% and is low cost of adoption, with mass production scheduled for 2025. N4C provides area-efficient underlying IP and design rules that are fully compatible with the widely adopted N4P, increasing yield by reducing chip size, providing a cost-effective option for value tier products to migrate to TSMC's next advanced technology node.
CoWoS, SoIC, and Wafer Systems (TSMC-SoW): TSMC's chip-on-substrate (CoWoS) allows customers to package more processor cores and high-bandwidth memory, becoming a key enabler of the artificial intelligence revolution (HBM) stacked side-by-side on an interposer. At the same time, our integrated system-on-chip (SoIC) has become the leading solution for 3D chip stacking, and customers are increasingly using CoWoS with SoICs and other components for ultimate system-in-package (SiP) integration.
With the wafer system, TSMC offers a revolutionary new option to implement a large number of chips on 300mm wafers, providing more computing power while taking up less data center space and increasing performance per watt by orders of magnitude. TSMC's first SoW product, a pure-play logic wafer based on integrated fan-out (InFO) technology, is now in production. The chip-on-wafer version that leverages CoWoS technology is scheduled to be ready by 2027 and will be able to integrate SoICs, HBMs, and other components to create powerful wafer-level systems with computing power comparable to data center server racks or even entire servers. Server.
Silicon photonic integration: TSMC is developing compact Universal Photonic Engine (COUPE) technology to support the explosive growth of data transmission brought about by the AI boom. COUPE uses SoIC-X chip stacking technology to stack electrical chips on top of photonic chips, providing the lowest impedance at the chip-to-chip interface and is more energy efficient than traditional stacking methods. TSMC plans to qualify the COUPE as a small pluggable product in 2025 and then integrate it into the CoWoS package as a co-packaged optical device (CPO) in 2026, introducing optical connectivity directly into the package.
Automotive Advanced Packaging: Following the launch of the N3AE "Auto Early" process in 2023, TSMC continues to meet automotive customers' demand for more computing power and meet highway safety and quality requirements by integrating advanced silicon with advanced packaging. TSMC is developing InFO-oS and CoWoS-R solutions for applications such as advanced driver assistance systems (ADAS), vehicle controls, and vehicle central computers, with the goal of achieving AEC-Q100 Grade 2 qualification by Q4 2025.
Reference Links
https://www.reuters.com/technology/tsmc-says-a16-chipmaking-technology-will-start-production-late-2026-2024-04-24/
https://finance.yahoo.com/news/tsmc-celebrates-30th-north-america-193000053.htm
Source | Semiconductor Industry Watch (ID: icbank) Synthesis
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