IT Home reported on January 7 that chip giant Intel recently won the industry's first ASML extreme ultraviolet (EUV) lithography machine with 0.55 numerical aperture (High-NA), which will help Intel achieve more advanced chip manufacturing processes in the next few years. In stark contrast, another giant, TSMC, is holding its ground and does not seem to be in a hurry to join the race for next-generation lithography technology. Industry analysts expect that TSMC may not adopt this technology until 2030 or even later.
Intel's High-NA EUV lithography machine will first be used to Xi learn and master the technology, and is expected to be used in the chip process node after 18A (1.8nm process) in the next two to three years. In contrast, TSMC has taken a more cautious approach, with analysts at China Renaissance Capital and SemiAnalysis arguing that TSMC may not adopt High-NA EUV technology until after the N1.4 process, which is expected after 2030.
"Unlike Intel's plan to introduce High-NA EUV to the 20A process at the same time as GAA transistors, we expect TSMC to introduce High-NA EUV after the N1.4 process, and not until 2030 at the earliest," said analyst Szeho Ng. ”
IT Home noted that Intel's aggressive process roadmap includes the introduction of RibbonFET full-ring-gate transistors and PowerVia backside power delivery networks starting at 20A (2nm class), then further optimization at 18A, and the adoption of High-NA EUV lithography machines at nodes after 18A to achieve lower power consumption, higher performance, and smaller chip size.
Today's mainstream EUV lithography machines use 0.33 numerical aperture (Low-NA) lenses, which are capable of achieving critical sizes of 13 to 16 nanometers in mass production, sufficient to produce 26 nanometer metal pitch and 25 to 30 nm interconnect pitch. This is sufficient for a 3nm-class process, but as the process scales down, the metal pitch will shrink to 18-21 nm (imec data), which will require techniques such as EUV double exposure, patterned etching, or High-NA single exposure.
Intel plans to introduce graphic etching starting at 20A, and then adopt High-NA EUV for nodes after 18A, which can reduce process complexity and avoid the use of EUV double exposure. However, the High-NA EUV lithography machine is much more expensive than the Low-NA EUV lithography machine, and there are a series of peculiarities such as the reduction of the exposure area by half.
Analysts believe that at least initially, the cost of High-NA EUV may be higher than that of Low-NA EUV double exposure, which is why TSMC is waiting and seeing for the time being. TSMC prefers to adopt proven technologies with lower costs to ensure product competitiveness.
"Although Low-NA EUV multiple exposures reduce capacity, they may still cost less than High-NA EUV," explains Szeho Ng, an analyst at China Renaissance Capital. This is in line with TSMC's strategy of targeting the mass market with the most cost-competitive technology. ”
TSMC began using EUV lithography machines in chip mass production back in 2019, a few months later than Samsung and a few years earlier than Intel. Intel wants to get ahead of Samsung and TSMC in the High-NA EUV space to gain certain technical and strategic advantages. If TSMC waits until 2030 or later to adopt High-NA EUV, will it be able to maintain its leadership in chip process technology?