If you talk about MOSFETs like this, modulus does not skip class (3)

If you talk about MOSFETs like this, the mode electricity does not skip class (1)

If you talk about MOSFETs like this, the mold electricity does not skip class (2)

In the second episode, we mentioned that Vgs are on the rise, and we can see that it is not "smooth sailing". He will produce a step. This episode explains the Miller Platform.

If you talk about MOSFETs like this, modulus does not skip class (3)

This step is the "Miller Step" or "Miller Platform" indicated.

Suppose an ideal reverse voltage amplifier with a gain of -Av is shown in the figure, connecting an impedance with a Z value between the amplifier's output and input. Define the input current as Ii (assuming the input current of the amplifier is 0) and the input impedance is Zin, so there is the following equation relationship,

As can be seen, the reverse voltage amplifier increases the input capacitance of the circuit and the amplification factor is (1+Av). This effect was first discovered by John Milton Miller and published in his 1920 book, hence the name Miller effect.

MOSFET, the schematic of adding parasitic capacitance can be represented by the following figure.

A MOSFET is a common source circuit :D rain as the output, source to ground, and Gate to input.

The interpolar capacitance gate-leakage capacitance Cgd, gate-source capacitance Cgs, and leakage-source cds of the MOS transistor can be determined by the following formula:

The values of the feedback capacitance Crs, input capacitance Ciss and output capacitance Coss of the MOS tube in the formula can be found in the MOS tube manual.

According to the mosfET's small-signal model, the MOSFET forms a reverse voltage amplifier whose equivalent circuit can be expressed as:

The gain of the voltage amplifier formed by the MOSFET needs to be judged according to its output and input resistance, and different MOSFETs will have different characteristics, so the gain is difficult to quantify.

In some cases, the magnification factor can reach hundreds of times.

Cdg forms a feedback loop (connecting the output port Drain and the input port Gate), and the Miller effect in the MOSFET is formed.

MoS activation process We mainly look at 3 signals: Vgs, Vds, Id

From the 0th hour, when Vgs begin to rise, Vds and Id remain the same, and the drive current ig charges Cgs in the process, and Vgs rises. All the way up to t1, Vgs rises to Vg(th), which is when the gate is turned on. Before the t1 hour, the MOS was in the cut-off zone.

From the moment of t1, the MOS will start to turn on, and the sign that it starts to turn on is that Id is about to start rising! So the DRAIN current Id of the MOS is slowly rising. The drive current is still charging Cgs during this time period. In the period from t1 to t2, Id is only quietly rising, and at t2 moment, Id rises to inductor current. Vds will drop slightly during the process of inductor current rise, because the falling di/dt creates some voltage drop on the stray inductor, so there will be some drop in the Vds on the side. From the t1 moment, the MOS entered the saturation zone.

When The Id rises to its maximum (t2), it immediately enters the Miller Platform period. The Miller platform is one where Vgs has remained virtually stationary for some time. As mentioned earlier, from the t1 moment, the MOS enters the saturation region, and there is a transfer characteristic in saturation: Id = Vgs * Gm. where Gm is transducer. Then it can be seen that as long as the Id is unchanged Vgs is unchanged. After the Id rises to the maximum, the Id is equal to the inductor current IL, and at this time it is in the saturation region, so Vgs will remain unchanged, that is, maintain the voltage of the Miller platform.

Id is the channel current, which is the current in the red part between the DS in the figure above. So when the drive current charges Cgs a little, Vgs increases Δvgs, then Id increases ΔId. So Vds will fall, that is, Vgd will fall, then ΔIgd = Cgd * ΔVgd/Δt, Igd will increase, so Vgs can hardly increase, can only be dynamically maintained near the Miller platform.

It can be seen that this is a negative feedback process. So Cgd is also called feedback capacitor.

Vgs↑→Id↑→ The current provided to Id via Cds↑→Vds↓→Vgd↓→Igd↑→Vgs rise slope↓

Before the t3 time, since CGS is much larger than CGD, the upward slope of VGS during this time period is mainly determined by CGS. When t3 starts, the VGD changes so that the equivalent capacitance value given to the CGD increases over time, you charge the capacitor, but the voltage on the other end of the capacitor changes rapidly.

The value of the capacitance to be charged by Vgs changes suddenly, causing its upward slope to be blocked, forming a step.

In the telecommunications industry and microwave circuit design, MOS tubes are commonly used to control the inrush current to achieve the purpose of slow start of the current. MOS tubes have the characteristics of low conduction impedance Rds_on and simple driving, and a small number of components can be added around to form a slow start circuit. Although the circuit is relatively simple, only after thoroughly understanding the relevant switching characteristics of the MOS tube can we have a deep understanding of this circuit.

Electronic engineers typically understand the turn-on process of a MOSFET based on the gate charge, as shown in Figure 1, which can be found in the MOSFET datasheet

MOS tubes are often used in design to design slow-start circuits. The MOS tube has the characteristics of low on-impedance Rds and simple driving, and a small number of components can be added around to form a slow start-up circuit. Typically, PMOS is used in the positive supply and NMOS is used in the negative supply.

The following figure is a -48V power supply slow start circuit built with NMOS, let's analyze the working principle of the slow start circuit.

1). D1 is an embedded diode to prevent excessive input voltage from damaging the secondary circuit;

2). The role of R2 and C1 is to achieve the stabilization delay function, in practical applications, R2 generally selects 20K ohms, C1 selects about 4.7uF;

3). The role of R1 is to provide a fast discharge channel for C1, requiring the voltage division value of R1 to be greater than the regulator value of D3, in practical applications, R1 is generally selected about 10K;

4). R3 and C2 are used to control the rising slope of the power-on current, in practical applications, R3 is generally selected about 200K ohms, and C2 takes a value of 10 nF to 100 nF;

5). The role of R4 and R5 is to prevent the MOS tube from self-oscillating, requiring R4, R5lt; < R3, R4 takes the value is generally between 10 and 50 ohms, R5 is generally 2K ohms;

6). The role of the embedded diode D3 is to protect the gate-source of the MOS tube Q1 from being broken down by high voltage; the role of D2 is to isolate the anti-shake delay circuit composed of R2 and C1 and the power-on slope control circuit composed of R3 and C2 after the MOS tube is turned on, so as to prevent the MOS gate charging process from being affected by C1.

Let's analyze the slow start principle of the circuit:

Assuming that the parasitic capacitance between the gate-source of the MOS tube Q1 is Cgs, the parasitic capacitance between the gate-drain is Cgd, the parasitic capacitance between the leakage-source is Cds, and the external gate-drain is connected in parallel with the capacitor C2 (C2gt; >Cgd), so the total capacitance of the gate-drain C'gd=C2+ Cgd, because the capacitance of Cgd is almost negligible relative to C2. So C'gd≈ C2, the opening voltage of the MOS tube gate is Vth, in normal operation, the MOS tube gate source voltage is Vw (this voltage is equal to the insertion voltage of the regulator D3), the time constant of the capacitor C1 charge t = (R1//R2//R3) C1, because R3 is usually much larger than R1, R2, so t ≈ (R1//R2) C1.

The following is a three-stage analysis of the working principle of the above voltage slow start circuit:

The first stage: -48V power supply to charge C1, charging formula is as follows.

Uc = 48 * R1 / (R1 + R2) [1-exp(-T/t)], where T is the time when the voltage of capacitor C1 rises to Uc, and the time constant t = (R1 //R2) C1. Therefore, the time required from power-up to MOS tube opening is: Tth=-t*ln[1-(Uc*(R1+R2)/(48*R1))]

The second stage: after the MOS tube is turned on, the drain current begins to increase, and its change rate is proportional to the rate of change of the MOS tube's cross-conductance and gate source voltage, the specific relationship is: dIdrain/dt = gfm *dVgs/dt, where gfm is the transconductance of the MOS tube, which is a fixed value, Idrain is the drain current, Vgs is the gate source voltage of the MOS tube, during this period, it is reflected in the constant control of the gate source voltage on the leakage source current, and the MOS tube is summarized as a voltage control device.

The third stage: when the leakage source current Idrain reaches the maximum load current, the leakage source voltage also reaches saturation, and at the same time, the gate source voltage enters the platform stage, and the voltage amplitude is set to Vplt. Since the leakage source current Ids remains constant during this time, the gate source voltage Vplt = Vth + (Ids/gfm), at the same time, because the fixed gate source voltage makes the gate current all through the feedback capacitor C'gd, the gate current is Ig = (Vw-Vplt)/(R3 +R5), because R5 is negligible relative to R3, so the Ig ≈ (Vw-Vplt)/R3. Because the gate current Ig ≈ Icgd, Icgd=Cgd*dVgd/dt. Because the gate source voltage remains constant during this time, the rate of change between the gate source voltage and the drain voltage is equal. Therefore: dVds/dt=dVgd/dt=(Vw-Vplt)/(R3*C2).

From this formula, it can be seen that the slope of the leakage source voltage change is related to the value of R3*C2, and for a system with a constant load, as long as the value of R3*C2 is controlled, the rising slope of the hot-swap inrush current can be controlled.