MStar 方案屏參配置

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【義 屏類型結構體定義 PanelType 】  文檔位置 ：《apiPNL.h 》
 /// A panel struct type used to specify the panel attributes, and settings from Board layout
 typedef struct
 {
 const char *m_pPanelName; ///< PanelName 屏的名稱
 //
 //  Panel output
 //
 MS_U8 m_bPanelDither :1; ///< PANEL_DITHER, keep the setting
 //Sub BK VOP_36(不同晶片，此值可能不一樣)，bPanelDither=1->0x2D05，
 bPanelDither=0->0x2D00
 APIPNL_LINK_TYPE m_ePanelLinkType :4; ///< PANEL_LINK
 //Sub BK VOP_44(不同晶片，此值可能不一樣)，LVDS=0x11，RSDS=0x00
 ///
 // Board related setting
 ///
 MS_U8 m_bPanelDualPort :1; ///< VOP_21[8], MOD_4A[1], PANEL_DUAL_PORT, refer to
 m_bPanelDoubleClk
 MS_U8 m_bPanelSwapPort :1; ///< MOD_4A[0], PANEL_SWAP_PORT, refer to "LVDS
 output app note" A/B channel swap
 MS_U8 m_bPanelSwapOdd_ML :1; ///< PANEL_SWAP_ODD_ML
 //蒙上灰
 MS_U8 m_bPanelSwapEven_ML :1; ///< PANEL_SWAP_EVEN_ML
 //蒙上灰
 MS_U8 m_bPanelSwapOdd_RB :1; ///< PANEL_SWAP_ODD_RB
 //缺色
 MS_U8 m_bPanelSwapEven_RB :1; ///< PANEL_SWAP_EVEN_RB
 //缺色
 MS_U8 m_bPanelSwapLVDS_POL :1; ///< MOD_40[5], PANEL_SWAP_LVDS_POL, for
 differential P/N swap
 //正負極性切換
 MS_U8 m_bPanelSwapLVDS_CH :1; ///< MOD_40[6], PANEL_SWAP_LVDS_CH, for pair
 swap
 //雙通道切換
 MS_U8 m_bPanelPDP10BIT :1; ///< MOD_40[3], PANEL_PDP_10BIT ,for pair swap
 MS_U8 m_bPanelLVDS_TI_MODE :1; ///< MOD_40[2], PANEL_LVDS_TI_MODE, refer to
 "LVDS output app note"
 //說明目前的屏是不是 TI mode
 ///
 // For TTL Only
 ///
 MS_U8 m_ucPanelDCLKDelay; ///< PANEL_DCLK_DELAY
 MS_U8 m_bPanelInvDCLK :1; ///< MOD_4A[4], PANEL_INV_DCLK
 MS_U8 m_bPanelInvDE :1; ///< MOD_4A[2], PANEL_INV_DE
 MS_U8 m_bPanelInvHSync :1; ///< MOD_4A[12], PANEL_INV_HSYNC
 MS_U8 m_bPanelInvVSync :1; ///< MOD_4A[3], PANEL_INV_VSYNC
 ///
 // Output driving current setting
 ///
 // driving current setting (0x00=4mA, 0x01=6mA, 0x02=8mA, 0x03=12mA)
 MS_U8 m_ucPanelDCKLCurrent; ///< define PANEL_DCLK_CURRENT
 //Sub VOP_？？[6:7](不同晶片，此值可能不一樣)，
 MS_U8 m_ucPanelDECurrent; ///< define PANEL_DE_CURRENT
 //Sub VOP_？？[4:5](不同晶片，此值可能不一樣)，
 MS_U8 m_ucPanelODDDataCurrent; ///< define PANEL_ODD_DATA_CURRENT
 //Sub VOP_？？[2:3](不同晶片，此值可能不一樣)，
 MS_U8 m_ucPanelEvenDataCurrent; ///< define PANEL_EVEN_DATA_CURRENT
 //Sub VOP_？？[0:1](不同晶片，此值可能不一樣)，
 ///
 // panel on/off timing
 ///
 MS_U16 m_wPanelOnTiming1; ///< time between panel & data while turn on power
 MS_U16 m_wPanelOnTiming2; ///< time between data & back light while turn on power
 MS_U16 m_wPanelOffTiming1; ///< time between back light & data while turn off power
 MS_U16 m_wPanelOffTiming2; ///< time between data & panel while turn off power
 ///
 // panel timing spec.
 ///
 // sync related
 MS_U8 m_ucPanelHSyncWidth; ///< VOP_01[7:0], PANEL_HSYNC_WIDTH
 MS_U8 m_ucPanelHSyncBackPorch; ///< PANEL_HSYNC_BACK_PORCH, no register setting,
 provide value for query only,
 ///< not support Manuel VSync Start/End now
 ///< VOP_02[10:0] VSync start = Vtt - VBackPorch - VSyncWidth
 ///< VOP_03[10:0] VSync end = Vtt - VBackPorch
 MS_U8 m_ucPanelVSyncWidth; ///< define PANEL_VSYNC_WIDTH
 MS_U8 m_ucPanelVBackPorch; ///< define PANEL_VSYNC_BACK_PORCH
 // DE related
 MS_U16 m_wPanelHStart; ///< VOP_04[11:0], PANEL_HSTART, DE H Start
 (PANEL_HSYNC_WIDTH + PANEL_HSYNC_BACK_PORCH)
 MS_U16 m_wPanelVStart; ///< VOP_06[11:0], PANEL_VSTART, DE V Start
 MS_U16 m_wPanelWidth; ///< PANEL_WIDTH, DE width (VOP_05[11:0] = HEnd = HStart +
 Width - 1)
 MS_U16 m_wPanelHeight; ///< PANEL_HEIGHT, DE height (VOP_07[11:0], = Vend =
 VStart + Height - 1)
 // DClk related
 MS_U16 m_wPanelMaxHTotal; ///< PANEL_MAX_HTOTAL. Reserved for future using.
 MS_U16 m_wPanelHTotal; ///< VOP_0C[11:0], PANEL_HTOTAL
 MS_U16 m_wPanelMinHTotal; ///< PANEL_MIN_HTOTAL. Reserved for future using.
 MS_U16 m_wPanelMaxVTotal; ///< PANEL_MAX_VTOTAL. Reserved for future using.
 MS_U16 m_wPanelVTotal; ///< VOP_0D[11:0], PANEL_VTOTAL
 MS_U16 m_wPanelMinVTotal; ///< PANEL_MIN_VTOTAL. Reserved for future using.
 MS_U8 m_dwPanelMaxDCLK; ///< PANEL_MAX_DCLK. Reserved for future using.
 MS_U8 m_dwPanelDCLK; ///< LPLL_0F[23:0], PANEL_DCLK ,{0x3100_10[7:0],
 0x3100_0F[15:0]}
 MS_U8 m_dwPanelMinDCLK; ///< PANEL_MIN_DCLK. Reserved for future using.
 ///< spread spectrum
 MS_U16 m_wSpreadSpectrumStep; ///< move to board define, no use now.
 MS_U16 m_wSpreadSpectrumSpan; ///< move to board define, no use now.
 MS_U8 m_ucDimmingCtl; ///< Initial Dimming Value
 MS_U8 m_ucMaxPWMVal; ///< Max Dimming Value
 MS_U8 m_ucMinPWMVal; ///< Min Dimming Value
 MS_U8 m_bPanelDeinterMode :1; ///< define PANEL_DEINTER_MODE, no use now
 E_PNL_ASPECT_RATIO m_ucPanelAspectRatio; ///< Panel Aspect Ratio, provide information
 to upper layer application for aspect ratio setting.
 /*
 *
 * Board related params
 *
 * If a board ( like BD_MST064C_D01A_S ) swap LVDS TX polarity
 * : This polarity swap value =
 * (LVDS_PN_SWAP_H<<8) | LVDS_PN_SWAP_L from board define,
 * Otherwise
 * : The value shall set to 0.
 */
 MS_U16 m_u16LVDSTxSwapValue;
 APIPNL_TIBITMODE m_ucTiBitMode; ///< MOD_4B[1:0], refer to "LVDS output app note" 當
 顔色不對的時候，就可以調整這個設定來試驗
 APIPNL_OUTPUTFORMAT_BITMODE m_ucOutputFormatBitMode; //Define panel output
 format bit mode.The default value is 10bit,because 8bit panel can use 10bit config and 8bit
 config.But 10bit panel(like PDP panel) can only use 10bit config.And some PDA panel is 6bit.
 MS_U8 m_bPanelSwapOdd_RG :1; ///< define PANEL_SWAP_ODD_RG
 MS_U8 m_bPanelSwapEven_RG :1; ///< define PANEL_SWAP_EVEN_RG
 MS_U8 m_bPanelSwapOdd_GB :1; ///< define PANEL_SWAP_ODD_GB
 MS_U8 m_bPanelSwapEven_GB :1; ///< define PANEL_SWAP_EVEN_GB
 //Sub MOD_??[2:5]，Odd_RG:bit3，Odd_GB:bit2，Even_RG:bit5，Even_GB:bit4
 /**
 * Others
 */
 MS_U8 m_bPanelDoubleClk :1; ///< LPLL_03[7], define Double Clock ,LVDS dual mode
 MS_U32 m_dwPanelMaxSET; ///< define PANEL_MAX_SET
 MS_U32 m_dwPanelMinSET; ///< define PANEL_MIN_SET
 //這個值會限定 FPLL LOCK 的範圍，也就是 LPLL_D5D6D7
 //1.reg_frame_lpll_en:LPLL_18[3]=0
 //2.reg_lpll_set調整：手動調整SET(BK31_1E,1F,20)值，觀察OSD是否異常找出Max/Min SET,
 寫入代碼需要除 2.
 APIPNL_OUT_TIMING_MODE m_ucOutTimingMode; ///<Define which panel output timing
 change mode is used to change VFreq for same panel 目前有三種選擇:E_PNL_CHG_DCLK,
 E_PNL_CHG_HTOTAL, E_PNL_CHG_VTOTAL, 後面兩者都是為了保持 DCLK 不變而修改
 HTOTAL/VTOTAL.
 MS_U8 m_bPanelNoiseDith :1; ///< PAFRC mixed with noise dither disable
 } PanelType ;
 【 名詞解釋 】
 Port swap:
 隻用在 dual port (FHD 在闆子上有兩組 LVDS)，将兩個 LVDS 互換
 Channel swap:
 一個 LVDS 裡面有很多 channel,
 6bit: CH0 CH1 CH2 CLK
 8bit: CH0 CH1 CH2 CLK CH3
 10bit: CH0 CH1 CH2 CLK CH3 CH4
 以 8bit 為例，Channel swap enable 後會有以下行為：
 CH0 <-> CH3、CH1 <-> CLK、CH2 <-> CH2 ，就是水準交換
 Polarity swap:
 每個 Channel 都有 Even(P)、Odd(M) 兩個極性，Polarity swap 就是将每個 channel 裡的兩個
 極性交換。以 8bit 為例：
 CH0P <-> CH0M，CH1P <-> CH1M，CH2P <-> CH2M，CLKP <-> CLKM，CH3P <-> CH3M
 【 配置介紹 】 文檔位置 ：《Panel.c 》
 (1)  屏的 接口類型設定
 如果屏的接口類型為 LVDS，則相關代碼如下：
 LINK_LVDS, //BOOL m_ePanelLinkType :2; //PANEL_LINK
 (2)  屏接口資料線的位數設定
 如果屏的接口資料線為 8 位雙口，則相關代碼如下：
 1, //BOOL m_bPanelDither :1; //PANEL_DITHER // 8/6 bits panel [0:6 1:8 bits panel]
 1, //BOOL m_bPanelDualPort :1; //PANEL_DUAL_PORT 0 // [0:單口 1:雙口]
 寄存器位址：MOD_4A[1]（0x3200 的 94 的第 1bit）
 (3)  屏的尺寸設定 （度 寬度 x  高度 ）
 如果屏的尺寸為 1024X768，則相關代碼如下：
 1024, //WORD m_wPanelWidth; //PANEL_WIDTH
 768, //WORD m_wPanelHeight; //PANEL_HEIGHT
 (4)  用于定義屏的高低 （MSB/LSM ） 位奇偶特性交換 ；
 0, //BOOL m_bPanelSwapOdd_ML :1; //PANEL_SWAP_ODD_ML
 0, //BOOL m_bPanelSwapEven_ML :1; //PANEL_SWAP_EVEN_ML
 (5)  用于定義屏的紅藍奇偶特性交換
 0, //BOOL m_bPanelSwapOdd_RB :1; //PANEL_SWAP_ODD_RB
 0, //BOOL m_bPanelSwapEven_RB :1; //PANEL_SWAP_EVEN_RB
 (6)  交換位選擇 （A ，B  口交換 ）
 0, // swap port
 如果此屏為單口,則這個值一定要置 1,雙口就無所謂,0 或 1 都可以,不影響.對應寄存器（0x3200 的
 94 的第 0bit）
 (7) TI_MODE  反就改這兩個
 1, //BOOL m_bPanelLVDS_TI_MODE :1; //PANEL_LVDS_TI_MODE
 對應寄存器（PANEL_LVDS_TI_MODE：MOD_40[2]即 0x3200 的 80 的第 2bit；）
 (8) 
 TI_8BIT_MODE, //8bit ti bit mode 屏的位數選擇，8 位，10 位，6 位，選擇對應的即
 可
 8bit ti bit mode： 0x3200 的 96 的第 0、1bit，
 0,1bit 空位 10bit 屏
 0 空，1 有是 8bit 屏
 0 有，1 有是 10bit 屏
 (9)  定義影像行方向和場方向的起始位置
 104+24, //WORD m_wPanelHStart; //PANEL_HSTART (PANEL_HSYNC_WIDTH
 + PANEL_HSYNC_BACK_PORCH)
 3+6, //WORD m_wPanelVStart; //PANEL_VSTART (PANEL_VSYNC_WIDTH +
 PANEL_VSYNC_BACK_PORCH)
 (HSTART 參照寄存器
 sub_bank=10, 102F08) PANEL_HSTART=((U16)PANEL_HSYNC_WIDTH+PANEL_HSYNC_
 BACK_PORCH)
 (VSTART 參照寄存器
 sub_bank=10, 102F0C) PANEL_VSTART=((U16)PANEL_VSYNC_WIDTH + PANEL_VSYNC
 _BACK_PORCH)
 (10) 此值相當于 HSTART 和 和 VSTART, 有時候屏未滿屏就可以改動此值. 
 24, //BYTE m_ucPanelHSyncBackPorch; //PANEL_HSYNC_BACK_PORCH
 6, //BYTE m_ucPanelBackPorch; //PANEL_VSYNC_BACK_PORCH
 (11) HTOTAL ： 機關時間行掃描的次數
 2048, //WORD m_wPanelMaxHTotal; //PANEL_MAX_HTOTAL
 1344, //WORD m_wPanelHTotal; //PANEL_HTOTAL
 1054, //WORD m_wPanelMinHTotal; //PANEL_MIN_HTOTAL
 此值非常關鍵，常影響屏的顯示效果，如上下缺線、白屏、閃動、VGA 某些模式拉絲、OSD 底部顯
 示缺邊等都可以調它)
 (HTOTAL 參照寄存器 sub_bank=10, 102F18, 102F19)
 (12) VTOTAL ： 機關時間列掃描的次數
 1024, //WORD m_wPanelMaxVTotal; //PANEL_MAX_VTOTAL
 806, //WORD m_wPanelVTotal; //PANEL_VTOTAL
 776, //WORD m_wPanelMinVTotal; //PANEL_MIN_VTOTAL
 （VTOTAL 參照寄存器 sub_bank=10, 102F1A, 102F1B）
 (13) 
 81, //DWORD m_dwPanelMaxDCLK; //PANEL_MAX_DCLK
 65, //DWORD m_dwPanelDCLK; //PANEL_DCLK
 50, //DWORD m_dwPanelMinDCLK; //PANEL_MIN_DCLK
 無信号時，顯示不正确，一般調整這裡可以解決,還有當 PC 是好的,其他信号源的台标顯示不正常閃動,
 就可以改動此值.
 PANEL_DCLK= (((U32)PANEL_HTOTAL*PANEL_VTOTAL*60)/1000000) Bank 31 的 20
 (14)  定義同 步信号的行寬 、 列高
 104, //BYTE m_ucPanelHSyncWidth; //PANEL_HSYNC_WIDTH
 3, //BYTE m_ucPanelVSyncWidth; //PANEL_VSYNC_WIDTH
 PANEL_HSYNC_WIDTH 和 PANEL_VSYNC_WIDTH 有時候圖象隻顯示了一半,就可以調這兩個,V
 方向和 H 方向.
 (15)  屏的時鐘和極性
 0x00, //BYTE m_ucPanelDCLKDelay; //PANEL_DCLK_DELAY
 0, //BOOL m_bPanelInvDCLK :1; //PANEL_INV_DCLK
 0, //BOOL m_bPanelInvDE :1; //PANEL_INV_DE
 0, //BOOL m_bPanelInvHSync :1; //PANEL_INV_HSYNC
 0, //BOOL m_bPanelInvVSync :1; //PANEL_INV_VSYNC
 這些是屏的時鐘和極性 ,比如有些屏某些位置會出現那種雪花點或躁點,你就可以試着調這裡.
 (16)  屏的上電/ 下電時序
 30, //BYTE m_ucPanelOnTiming1; //PANEL_ON_TIMING1 // time between panel & data
 while turn on power
 500, //BYTE m_ucPanelOnTiming2; //PANEL_ON_TIMING2 // time between data & back li
 ght while turn on power
 150, //BYTE m_ucPanelOffTiming1; //PANEL_OFF_TIMING1 // time between back light & d
 ata while turn off power
 30, //BYTE m_ucPanelOffTiming2; //PANEL_OFF_TIMING2 // time between data & panel w
 hile turn off power
 當時序不比對的時候可能出現上/下電白屏
 (17) 屏的電流
 // driving current setting (0x00=4mA, 0x01=6mA, 0x02=8mA, 0x03=12mA)
 0x01, //BYTE m_ucPanelDCKLCurrent; //PANEL_DCLK_CURRENT // DCLK current
 0x01, //BYTE m_ucPanelDECurrent; //PANEL_DE_CURRENT // DE signal current
 0x01, //BYTE m_ucPanelODDDataCurrent;//PANEL_ODD_DATA_CURRENT//odd data c
 urrent
 0x01,
 //BYTEm_ucPanelEvenDataCurrent;//PANEL_EVEN_DATA_CURRENT//evendata current
 有些屏需要的電流要大,你就可以在這裡修改
 (18) 
 MS_U32 m_dwPanelMaxSET; ///< define PANEL_MAX_SET
 MS_U32 m_dwPanelMinSET; ///< define PANEL_MIN_SET
 SET=216*5242888*8/(7*DCLK)
 注意 DCLK 的值要設定為單組的 DCLK 的值，即如果是雙位屏，要除以 2
 (19)  調節三星屏的時候以及 6BIT  屏有時要用到
 OUTPUT_10BIT_MODE, //10bit ti bit mode
 這個調節三星屏的時候以及 6BIT 屏有時要用到 具體寄存器為：0x3200 的 92 的 bit6,bit7
 (20)  選擇屏的 clock  數
 1, // double clock
 如果是雙位屏要設定為 1，機關屏選 0，否則屏會顯示不正常,0x3100 的 06
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