本文是我學習AFE IP子產品手冊時的log。希望對大家有幫助！
參考手冊
Chapter 31：
Analog Front End
31.1.1 Overview
AFE 內建子產品由 ΣΔ ADCs, PGA, filtering and phase compensation blocks 組成，負責測量相位電壓 相位電流 中心點電流
31.1.2 Clock Sources
P81
PLL can optionally drive both MCGCLKOUT and clock to AFE;however, for best accuracy in AFE, PLL should drive clock to AFE only).
When PLL is driving AFE clock, this clock should not be used for any other module including the core, bus, flash and other peripherals as this is necessary to ensure good accuracy from AFE. If PLL clock is driving core, bus and flash clocks, there could be some degradation in performance from AFE.
The AFE can optionally be clocked from MHz oscillator clock (provided it is less than 32 MHz - for crystal clock and 50 MHz - externally supplied clock) and FLL clock when AFE accuracy is not important (PLL can be disabled to save power in these cases).
*最好不用FLL做AFE的時鐘，不準确
*PLL做AFE時鐘時，不要讓PLL再做core bus flash這些的時鐘，不然AFE的性能精度都會下降
*直接由外部晶振提供時，crystal clock < 32 MHz
P563
下面的SIMAFECLK就是上圖的AFE_CLK。
• 4 MHz IRC from MCG
• SIMAFECLK(SIMAFECLK就是上 上圖的AFE_CLK。）
• Quad Timer channel 0 output
• Externally supplied clock (30 kHz to 50 MHz) via AFE_CLK pin
• This pin can additionally be used to interface clock port of external modulators
(which provide clock output with data). 通過上圖的AFEOUTCLKSEL選擇
• Prescaler on AFE will divide this external clock to generate required range of
clock at modulator input (30 kHz to 6.5 MHz).
The above clock sources are available in all MCU power modes where AFE can work,
except for VLPS where PLL cannot work. Hence for operating AFE in VLPS, a different
clock source would be required.
上面這些時鐘源在所有AFE能夠工作的電源模式下都可用。 但是在VLPS電源模式下 PLL不能夠被使用，是以如果AFE工作在VLPS模式下的話，需要選擇其他的時鐘源。
The selected clock source is prescaled down to the AFE modulator clock operating range
(30 kHz to 6.5 MHz in Normal mode, and less than 1.6 MHz for Low Power mode)
before enabling AFE operations. The Prescaler divides down the selected clock in powers
of 2 (that is 1, 2, 4, 8, 16, 32, 64, 128 and 256). It is important to divide the selected clock
by at least 2 to compensate for any duty cycle variations during muxing and clock
propagation.
在使能AFE操作之前，需要将選擇的時鐘源分頻到AFE子產品的工作時鐘範圍(30 kHz to 6.5 MHz in Normal mode, and less than 1.6 MHz for Low Power mode)。至少兩分頻來補償由于多路複用和時鐘傳播引起的占空比的變化。
NOTE
• The externally supplied clock is routed directly from the
AFE_CLK pad to the AFE prescaler.
• The clock source selection is one time selection and cannot
be changed on the fly. AFE needs to be disabled to change
the clock and prescaler.
• Using any clock source other than the PLL output clock or
oscillator clock will not guarantee AFE performance.
• Refer to the Clocking chapter for details on generation of
MCGPLLCLK and muxing options.
• All AFE channels should run on the same clock. The clock
selection is done via register bits in AFE and is common to
all AFE channels.
注：
• 外部時鐘直接從AFE_CLK pad 連到 AFE prescaler.
• 時鐘源選擇不能再AFE子產品工作時改變，如果要改變 需要先失能AFE
• 除了PLL輸出時鐘和晶振時鐘，其他的時鐘源都不能保證AFE的性能。
•
• 是以AFE通道都應運作在同一個時鐘上。
The following figure shows the clocking strategy for the AFE. By configuring the
SIM_CTRL_REG[AFEOUTCLKSEL]bit, user can select the AFE clock before or
prescaler and output this clock to AFE_CLK pin and XBAR.
通過配置SIM_CTRL_REG[AFEOUTCLKSEL]bit 可以選擇輸出在分頻之前還是之後
The selected clock is common to all AFE channels (0-3) even if some of the channels use
an external modulator. When AFE is disabled, the clock sources should be gated or
disabled to save power.
即使一些通道使用的是外部的modulator，選擇的時鐘對是以AFE通道對一樣。AFE失能時記得關閉時鐘源以省電。
31.2 Introduction
The Analog Front End or AFE is an integrated module that is comprised of four sigmadelta
ADCs (all with PGA) referred to as channels and input voltage reference. The
converters are based on second-order oversampling sigma-delta modulators and digital
decimation filters with selectable over sampling ratio up to 2048. Additional filtering can
be done in software.
31.3 Features
• Four 24-bit (after averaging) sigma-delta ADC with PGA
• Option to bypass/disable the PGA
• PGA with 7μV sensitivity (PGA gain = 1 V/V), 7 μV sensitivity (PGA gain = 32
V/V)
• Voltage measurement can operate in both differential and single ended mode. For
single ended operation, the differential pin shall be grounded externally on board.
• Input common-mode voltage range of 0 to 0.8V
• Full Operating Voltage Range – 2.7V to 3.3V
• Output sampling rates 3 KHz, 6 KHz, 12 KHz, 24 KHz, 48 KHz, and 96 KHz.
• Software selectable analog gain 1x, 2x, 4x, 8x, 16x, 32x
• Software selectable on-chip reference voltage and common mode voltage generation
(1.2 V)
• Software selectable internal or external reference
• ±250 mVp (1 Vpp differential, 0.5 Vpp single ended) input range for all AFE inputs
• Support for interfacing to external modulators when AFE bypass option is enabled.
• Digital logic enables synchronized start of all AFE blocks
• Interrupt and DMA request on Conversion Complete.
• Asynchronous DMA request generation to transfer data in deep sleep(STOP) mode.
• Both Hardware and software trigger can be used to initiate data conversion.
• 30kHz to 6.5 MHz Modulator input frequency.
• Selectable low-power conversion mode.
• Selectable low-power conversion mode.
• Implements phase compensation Upto 0-6.0 degree @(OSR = 2048 & 50 Hz input)
• Allows dynamic change of phase shift without interrupting sampling cycles
• Software selectable clock option for modulator clock.
PGA:可程式設計增益放大器(Pmgrammable Gain Amplifier)。
随着計算機的應用，為了減少硬體裝置，可以使用可程式設計增益放大器(PGA:Pmgrammable Gain Amplifier)。它是一種通用性很強的放大器，其放大倍數可以根據需要用程式進行控制。采用這種放大器，可通過程式調節放大倍數，使A/D轉換器滿量程信号達到均一化，因而大大提高測量精度。所謂量程自動轉換就是根據需要對所處理的信号利用可程式設計增益放大器進行倍數的自動調節，以滿足後續電路和系統的要求。 可程式設計增益放大器有兩種——組合PGA和內建PGA。
Decimation Filter ：數字降采樣濾波器
sigma-delta modulators：∑—Δ調制器
31.5 AFE Clocking
The maximum operational frequency of the AFE modulator clock is 6.5 MHz. For
optimum performance the clock should have minimum jitter with 50% (approx) duty
cycle. Four possible clock sources (selected by programming CLS[1:0]) are provided to
be used as MOD_CLK.A clock divider is in place to further divide down the MOD_CLK
frequency for low power application. The AFE_CKR[DIV] field selects the divide ratio
to generate final mod_clk to AFE.
Fmod_clk = Fclk / 2^ DIV where Fclk is the input clock to divider. The modulator clock
frequency must be in the range of 30KHz -6.5 MHz. The clock divide ratio has a range
from 1 - 256
Below digram depicts the AFE clocking implementation.
DIV N 之前最大頻率6.5M
31.6 OSR Select
The oversampling ratio (OSR) is the ratio of the modulator clock frequency (fSDMCK)
to the output sample frequency. For example: a 6.144 MHz modulator clock with an OSR
= 256 yields an output sample rate of 24 kHz. The OSR field selects the OSR which can
be 64, 128, 256, 512, 1024, or 2048. A higher OSR produces a lower sample rate and
narrower bandwidth.
過采樣率 是 modulator clock frequency 和output sample frequency 的比值。
過采樣率（取樣比） 可以選擇 64, 128, 256, 512, 1024, or 2048. 過采樣率越高，越低的采樣率和更窄的帶寬。
31.7 Analog Gain Select
The AGN field selects the front end analog gain applied to the input signal. The
selectable gains are x1, x2, x4, x8, x16, x32. Higher gain settings reduce the full scale
input of the converter.
31.9 Power Modes
AFE supports four power modes
• Normal Run Mode
• Low Power Run Mode
• Wait Mode
• Stop Mode
支援四種功耗模式
31.9.1 Normal Run Mode
In Normal run mode AFE is fully functional and maximum clock frequency of operation
can be up to 6.5 MHz.In this mode PGA can be optionally bypassed to achieve further
low power.
正常運作模式下，最大工作時鐘可達6.5MHz。 在這個模式下，可以選擇旁路PGA來減小功耗。
31.9.2 Wait Mode
Operation of the AFE is not affected by the MCU entering wait mode. If conversions
have already been initiated before entering wait mode, conversions will continue in wait.
Conversions can be initiated while the MCU is in wait mode by means of the hardware
trigger. Since the CPU is inactive in wait, a software trigger cannot initiate conversions
while in wait. The system must continue to produce the modulator clock in order for
conversions to continue during wait. If enabled, the AFE interrupt will wake the MCU
from wait mode.
AFE的運作不會因為MCU進入等待模式而受到影響。如果轉換在進入等待模式之前已經初始化完畢，轉換過程會在wait模式下繼續執行。 當MCU在等待模式下時，可通過硬體觸發的方式來初始化轉換。由于在等待模式下CPU停止運作，是以軟體觸發無法初始化轉換。 系統必須能夠繼續提供調制器時鐘來保證wait模式下繼續進行轉換過程。如果使能了，AFE的中斷可以在wait模式下喚醒MCU。
31.9.3 Low Power Run Mode
When the LPM_EN bit is set the AFE enters Low power run mode. In this mode the
maximum frequency of the mod_clk should be less than equal to 1.6 MHz where 768
KHz is the nominal value. Setting this mode reduces the current consumption of
ADC.When the device enters Very Low power mode(VLP) then AFE automatically
enters into low power mode.
在低功耗運作模式下，mod_clk 最大隻能小于等于1.6MHz，768KHz是标稱值。這種模式下ADC的電流消耗會變少。當系統進入VLP模式時，AFE會自動進入低功耗模式。
31.9.4 STOP Mode
When the device enters stop mode the ADC can be fully operational if the mod_clk is
present. AFE is capable to wakeup the device from STOP mode through asynchronous
interrupt. AFE is also capable to generate asynchronous DMA request to DMA controller
in absence of bus clk. The asynchronous DMA request only gets asserted in STOP mode
and remains asserted until synchronous DMA gets asserted in presence of system clock
enabled by System Wake-up unit.
當系統進入停止模式時，如果mod_clk時鐘還在的話，ADC依然能夠滿血運作。AFE能夠通過異步中斷将系統從STOP模式下喚醒。
即使在沒有總線時鐘的情況下，AFE也能夠向DMA控制器發出異步請求。？？？？？？？？？？？？？？？？？
31.10 Functional Description
The main components of AFE are analog modulators,programmable gain
amplifiers,decimation filters and digital logic comprised of programming model to
configure AFE,store result register,clock generation,trigger generation logic and
interrupt,dma capability.Modulator clock is provided by the system or external source
which is internally prescaled to the correct operating range for AFE.The modulator
samples the analog input signal and generates a digital output code at this clock rate.The
high rate modulator output is filtered and decimated by the decimation filters which
produce 24-bit output samples at a lower rate.Due to the latency of the decimation filter,
each time decimation filter is enabled or resynchronization happens it takes three output
samples to reach steady state in which fully valid samples are produced.This is the first
valid AFE conversion data after it is enabled or re-synchronized.
AFE的主要子產品有 analog modulators,programmable gain amplifiers,decimation filters
and digital logic(programming model to configure AFE,store result register,clock generation,trigger generation logic and
interrupt,dma capability)
PGA:可程式設計增益放大器(Pmgrammable Gain Amplifier)。
Decimation Filter ：數字(降采樣)濾波器
sigma-delta modulators：∑—Δ調制器
調制器的時鐘即可來自系統又可來自外部源，前提是内部預分頻到保證AFE正常工作的範圍内。 調制器采樣模拟輸入信号并産生數字輸出。
高速率的調制器輸出經過數字濾波器輸出24bit的低速率采樣結果。 由于數字濾波器的延時，每次在數字濾波器啟動或者再同步發生時，我們需要等待三個采樣輸出之後才能進入穩定輸出狀态（得到有效的采樣輸出）。此時得到的轉換資料才是有效的。
31.10.1 Start Up
The AFE is disabled by default or when the enable bit in corresponding AFEx_CFR
register is cleared. After reset user should enable all required SD-ADCs (SD_MOD_ENx
=1), PGAs and Decimation filter and then enbale the global control by setting MSTR_EN
bit. Once the configuration is done, AFE will wait for the conversion trigger to start
conversion. Once software/hardware (according to TRGx bit) trigger is received the
enabled ADC modules go through a ‘n’ modulator clock cycle start-up period where ‘n’
should be programmed (AFE_CR[STARTUP_CNT]) to achieve at-least 20 μs startup
time. Once this start-up has completed the RDY flag is set and conversions begins. The
software/hardware trigger signal is ignored during the start-up period.
配置AFE_CR[STARTUP_CNT]，保證至少20us的啟動時間
當接收到軟體或硬體觸發信号後，需要等待 start-up period 後，RDY标志位置位，轉換開始。
啟動時間内，軟硬體觸發信号都會被忽略。
31.10.2 Conversion Control
Once a conversion is triggered, the modulator,decimation filters are enabled and the
COCx flag is set after the conversion completes.In continuous conversion mode (CC=1),
conversions continue after the first sample. Using continuous conversion mode, a series
of conversions can be made on at the rate of one sample per OSR modulator clock
cycles.In single conversion mode each conversion requires a conversion trigger.
31.10.2.1 Triggering Conversions
Both software and hardware trigger mode is supported to initiate conversion.
• In software trigger mode (TRG=0), writing to AFE_CR[SFT_TRGx] bit will cause a
conversion to initiate or restart while a conversion is already in progress.
• In hardware trigger mode (TRG=1), a conversion is initiated/restarted by the
assertion of the hardware trigger input signal. The hardware trigger input is ignored
during the start-up period. The hardware trigger source is device specific.
NOTE
Conversion modes are mentioned in details in later section.
31.10.2.2 Conversion Complete
When a conversion completes, the new sample value is transferred to the AFEx_RR
register and the corresponding COCx bit is set. Several other actions can also be enabled
when a conversion completes,for example if the INT_EN bit is set, the interrupt request is
asserted, if the DMA bit is set the DMA request is asserted .
The COC bit and interrupt request are all cleared by reading the AFEx_RR register.If the
COC bit is still set when a conversion completes and the new sample comes it will
overwrite the old sample and set the overflow flag.
采集完成後，新的采樣值被傳送到AFEx_RR寄存器中，相應得轉換完成标志置位。
讀AFEx_RR寄存器中的值，轉換完成标志COC和中斷請求标志就會被清除。如果COC标志還未被清零時，又一次轉換結束，新的采樣值将會覆寫舊的采樣值，此時覆寫标志overflow flag 将會置位。
31.10.2.3 Total Conversion Time
• In Single conversion mode the total conversion time for a single conversion is
(AFE_STARTUP+ 3 x OSR x MOD_CLK) after the trigger event.
• In Continuous conversion mode the conversion time for the first 24 bit sample is
(AFE_STARTUP + 3 x OSR x MOD_CLK) after the trigger event,however the
subsequent 24bit samples are available after (OSR x MOD_CLK) cycle.
• During any continuous conversion if user opts to resync any conversion by providing
trigger , the first conversion result after the resync operation will be available after
(AFE_STARTUP time + 3xOSRxMOD_CLK) cycle.
• However if user opts for run time phase compensation for any channel after the
current conversion by adjusting Phase delay registers and setting dly_ok signal,the
conversion result won’t take 3 decimator clock cycle(3xOSRxMOD_CLK).Instead
the sampled data will be available after OSRxMOD_CLK cycle.
NOTE
There can be latency of 2-3 mod_clk cycle in conversion time
due to synchronization of asynchronous trigger.
總得轉換時間
第四點: 如果使用者選擇在目前轉換之後對任意通道進行相位補償（通過調整相位延時寄存器和設定dly_ok信号），采樣資料将在一個 OSRxMOD_CLK cycle 後就會有效。
注：
由于對異步觸發信号的同步，轉換時間會存在2-3個mod_clk的延時。
31.10.2.4 Timing Diagram
Single conversion:
Continuous conversion:
Continuous conversion with phase delay:
Continuous conversion with phase delay: Val1 of channel0, 1 are available after
(STARTUP_TIME + 3xOSR) mod_clk cycle Val2 of channel0, 1 are available after OSR
mod_clk cycle. Val3 of channel1 is available after (OSR+5) mod_clk cycle which
signifies input sample of second channel is delayed by 5 mod_clk cycle w.r.t channel0.
Val4, Val5 of channel1 are available after(OSR+8) mod_clk cycle which signifies input
sample of second channel is delayed by 8 mod_clk cycle w.r.t channel0.
Resynchronization of conversion:
31.10.2.5 Aborting Conversion
To abort a conversion in progress, disable the ADC by clearing SD_MOD_ENx bit.To
abort/disable all the conversions globally ,clear MSTR_EN register.The AFEx_RR
register will retain the value of the last completed conversion.
通過清除 SD_MOD_ENx bit 來 終止正在進行的一次轉換。
通過清除MSTR_EN register 來終止所有轉換。
AFEx_RR register 将保持最後一次完成轉換的AD值。
31.10.3 Modes of Conversion
AFE supports both single and continuous conversion mode where each channel can
independently be either in single or continuous conversion mode. Below are the steps
needed to initiate various conversion supported by AFE.
無論是單次轉換模式還是循環轉換模式，所有通道都彼此獨立。
下面是初始化多種轉換的步驟
31.10.3.1 Single Conversion
By default AFE is in single conversion(AFE_CR[CC]=0) mode.After each single
conversion modulators,PGAs and Filters get automatically disabled.User should set
SW_TRG or hardware trigger to re-initiate another single conversion.Due to latency of
decimation filter the valid conversion data becomes available after (AFE_STRUP +
3*OSR) mod_clk cycle.The different approaches to trigger a single conversions are
mentioned below.
預設配置下，AFE出于單次轉換模式。
每次轉換結束，modulators PGAs Filters 都會自動失能。
使用者需要通過軟體觸發或硬體觸發來重新啟動下一次單次轉換。
由于數字濾波器的延時，轉換資料在AFE_STRUP +3*OSR 個 mod_clk cycle 後才有效。
下面是軟硬體觸發的配置說明
31.10.3.1.1 Software Trigger
31.10.3.1.2 Hardware Trigger
• Once the AFE is configured properly,an external pulse trigger will enable all
Modulators,PGAs,Filters and its startup period.After the startup period the
conversion result will be available after 3*OSR mod clock cycle.
31.10.3.2 Continuous Conversion
Setting AFE_CR[CC] bit prior to any conversion,initiates continuous conversion.The
different approaches to trigger a continuous conversions are mentioned below.
在是以轉換之前設定 AFE_CR[CC] bit為1，啟動連續轉換模式。
連續轉換模式的觸發方式描述如下：
31.10.3.2.1 Soft Trigger
31.10.3.2.2 Hardware Trigger
31.10.3.2.3 On-the-fly Phase Delay Adjustment
運作時相位延時（不同通道之間的相位延時）調整
While continuous conversion is in progress, on-the-fly delay adjustment between
channels can be done using these steps.、
• If phase compensation is required between the channels, configure the phase
difference (in terms of mod_clk cycle) by programming CHx_DR register.
• Select AFE_CR[DLY_OK] bit.
• Internal phase synchronization will be initiated for the next sample with the adjusted
delay programmed in CHx_DR register.
• If Conversion complete DMA is enabled then AFE will generate dma_request to
DMA controller after each valid conversion.
• If DMA is disabled and Conversion complete interrupt is enabled AFE will generate
interrupt and set COCx flag after each valid conversion.
• To disable continuous conversion globally for all channels, clear
AFE_CR[MSTR_EN] bit or disable individual channels Filter(DEC_ENx = 0 or
SD_MOD_EN = 0).
• While clearing AFE_CR[MSTR_EN] the last conversion result may give invalid
result.
31.10.4 Independent Control for Conversion
Conversion control configuration for all channels are completely independent to each
other to enhance the flexibility of AFE functionality.Hence user can configure one
channel for single conversion with software trigger mode where the other channels are in
continuous conversion mode triggered by either software or external hardware
source.Each channel has independent conversion complete indicator to the system.
通道之間彼此完全獨立，任意配置各自的轉換模式和觸發模式。每個通道都有獨立的狀态标志。
31.11 Decimation Filter
The decimation filter is a digital block that low-pass filters and decimates the high rate,
single bit sigma-delta modulator output to generate a lower rate 24-bit output signal. The
decimation filter supports over-sampling ratios (OSR) from 64 to 2048. It includes a third
order sinc filter.The sinc filter down samples the signal by the selected OSR.The sinc
filter output it scaled based on the OSR and then limited to produce a 24-bit signed, two’s
complement output which is stored in corresponding channel’s result register.
P572
31.11.1 Sampling Phase Control
When conversion is either HW or SW triggered, regardless of the operation mode, or in
continuous mode when new conversion starts then the phase between two or more
channels may be adjusted ,if user opts to adjust the sampling phase during filtering
operation to allow a precise sampling phase offset to be established and adjusted between
two or more channels it is required to update the delay register and set dly_ok at the end
to indicate the update of delay register. The delay registers set the initial phase offsets for
the channels when they are enabled. When the channels are running, the delay registers
are used to add delay to a channel. However the value of the delay register comes into
effect from the next sampling period after the current conversion is completed.For
example. the set of initial values in delay register are 0,5,10 and 8 for the four channels
and we want the final sampling phase delays to be 0,4,12,10. The delays of 1,0,3,3 are
updated in corresponding channel’s delay register which yield the 1,5,13,11 as absolute
delays and have the desired relative delay of 0,4,12,10 respectively.
等目前的轉換完成後，delay register 裡的值在下一次采樣周期裡才會有效。
初始值0,5,10， 8
想要的delay值 0,4,12,10.
？？？？？？？？
31.11.2 Frequency response
31.12 Modulator Bypass Mode
Modulator bypass mode is set by setting CHn_CR[BYP_MOD] bit. When set, the analog
part of the corresponding channel gets automatically disabled.The SINC3 Filter and
phase shift compensation block can be used in connection with an external sigma delta
modulator. The clock to external sigma delta modulator can be derived from on-chip
modulator clock. On the contrary, external sigma delta modulator binary output stream is
routed to internal decimation filter.In such a way, any external sigma delta modulator can
be used for the measurement along with other built-in sigma delta modulators.The clock
is provided either by on-chip mod_clk source or any external clock input which after
division fed to decimation filter as well as external Modulator through mod_clk_out
port.The module also supports independent control for each channel.So one channel can
be used in bypass mode,while the others are in modulator engage mode.
sigma delta modulator調制器旁路模式，其實就是直接用外部的sigma delta modulator。外部的
sigma delta modulator的時鐘可以由晶片内部的調制器時鐘輸出提供。外部的sigma delta modulator
二進制資料流直接傳給内部的數字濾波器。
通道彼此獨立，一個通道可以處于bypass模式，另一個處于非bypass模式。
4.
定下需要測試的例子
fsl_afe_ex_single_conversion_software_interrupt :
fsl_afe_ex_single_conversion_software_rolling :
fsl_afe_ex_single_conversion_hardware_interrupt :
fsl_afe_ex_continuous_conversion_software_interrupt :
Continuous conversion with phase delay:
5.
fsl_afe_ex_single_conversion_hardware_interrupt :
如何設定硬體觸發源：
用PTD2連到XBAR_IN3,再連到AFE Channel 0 Trigger上。
a.
PORT_SetPinMux(PORTD, 2U, kPORT_MuxAlt4); //XBAR_IN3
PORT_SetPinMux(PORTE, 4U, kPORT_MuxAsGpio);
b.
gpio_pin_config.pinDirection = kGPIO_DigitalOutput;
gpio_pin_config.outputLogic = 0;
GPIO_PinInit(TEST_OUTPUT_GPIO_BASE, TEST_OUTPUT_PIN, &gpio_pin_config);
PE4 數字輸出
c.
//AFE配置成硬體觸發
afeChnExampleStruct.enableHardwareTrigger = true;
AFE_SetChannelConfig(DEMO_AFE_INSTANCE, DEMO_AFE_CHANNEL, &afeChnExampleStruct);
6.
Low power
在低功耗運作模式下，mod_clk 最大隻能小于等于1.6MHz，768KHz是标稱值。這種模式下ADC的電流消耗會變少。當系統進入VLP模式時，AFE會自動進入低功耗模式。
a.
/* Select clkSrc for AFEclk */
CLOCK_SetAfeClkSrc(2U);
闆子上是8M的外接晶振，需要八分頻才能小于1.6M