記verilog實作counter的兩種if-else表達方式

第一種：

always @(posedge clk or negedge rst_n) begin
        if(!rst_n)
            counter_ndl <= 16'd0;
        else 
            if(cs==WR_SEQ)
                if(fifo_pop_req)
                    counter_ndl <= counter_ndl - 16'd1;
                else
                    counter_ndl <= counter_ndl;
            else if(cs==BC_CIRC && counter_ndl==16'd0 && ch_circ==1'b1)
                    counter_ndl <= ch_ndl;
    end
           

第二種：

always @(posedge clk or negedge rst_n) begin
        if(!rst_n)
            counter_ndl <= 16'd0;
        else if(cs==WR_SEQ && fifo_pop_req)
            counter_ndl <= counter_ndl - 16'd1;
        else if(cs==BC_CIRC && counter_ndl==16'd0 && ch_circ==1'b1)
            counter_ndl <= ch_ndl;                  //load count value
    end
           

顯然第二種更好。

第一種格式類似于人思維的直接表達，沒經過加工和整理，初學者的常見寫法，甚至有些多年經驗的工程師也會出現這種寫法。

第二種格式精确的概括了counter的兩種狀态：計數狀态、加載初始值狀态，并概括了兩種狀态的條件，更加接近電路的真實表達。

另附兩個例子：

第一種：

always @(posedge clk or negedge rst_n) begin
        if(!rst_n)
            counter_pop <= 3'd0;
        else 
            if(cs==WR_SEQ)
                if(fifo_pop_req)
                    counter_pop <= counter_pop + 3'd1;
                else
                    counter_pop <= counter_pop;
            else
                    counter_pop <= 3'd0;
    end
           

第二種：

always @(posedge clk or negedge rst_n) begin
        if(!rst_n)
            counter_pop <= 3'd0;
        else if(cs==WR_SEQ && fifo_pop_req)
            counter_pop <= counter_pop + 3'd1;
        else if(cs!=WR_SEQ)
            counter_pop <= 3'd0;
    end