目錄
5 bit LFSR
3 bit LFSR
32 bit LFSR
A linear feedback shift register is a shift register usually with a few XOR gates to produce the next state of the shift register. A Galois LFSR is one particular arrangement where bit positions with a "tap" are XORed with the output bit to produce its next value, while bit positions without a tap shift. If the taps positions are carefully chosen, the LFSR can be made to be "maximum-length". A maximum-length LFSR of n bits cycles through 2n-1 states before repeating (the all-zero state is never reached).
The following diagram shows a 5-bit maximal-length Galois LFSR with taps at bit positions 5 and 3. (Tap positions are usually numbered starting from 1). Note that I drew the XOR gate at position 5 for consistency, but one of the XOR gate inputs is 0.
Module Declaration
module top_module(
input clk,
input reset, // Active-high synchronous reset to 5'h1
output [4:0] q
); 線性回報移位寄存器是通常帶有幾個XOR門的移位寄存器，用于産生移位寄存器的下一個狀态。 Galois LFSR是一種特殊的移位寄存器，其中将帶有“抽頭”的位位置與輸出位進行異或運算以産生其下一個值。 如果仔細選擇抽頭位置，則可以将LFSR設為“最大長度”。 n位的最大長度LFSR在重複之前循環經過2n-1個狀态（永遠不會達到全零狀态）。
下圖顯示了一個5位最大長度的Galois LFSR，在位置5和3處有抽頭（抽頭位置通常從1開始編号）。 請注意，為保持一緻性，我在位置5處繪制了XOR門，但XOR門輸入之一為0。
說到底，就是一個移位寄存器，隻不過某些輸入不是上一級觸發器的輸出，而是有可能和其他級的輸出進行了異或作為目前的輸入；
給出設計（與0異或等于本身）：
module top_module(
input clk,
input reset, // Active-high synchronous reset to 5'h1
output reg [4:0] q
);
always@(posedge clk) begin
if(reset) q <= 5'h1;
else begin
// q[4] <= q[0];
// q[3] <= q[4];
// q[2] <= q[3]^q[0];
//q[1] <= q[2];
//q[0] <= q[1];
q <= {q[0],q[4],q[3]^q[0],q[2:1]};
end
end
endmodule
Write the Verilog code for this sequential circuit (Submodules are ok, but the top-level must be named top_module). Assume that you are going to implement the circuit on the DE1-SoC board. Connect the R inputs to the SW switches, connect Clock to KEY[0], and L to KEY[1]. Connect the Q outputs to the red lights LEDR.
module top_module (
input [2:0] SW, // R
input [1:0] KEY, // L and clk
output [2:0] LEDR); // Q
下面對上面的電路進行設計：
首先，可以看出有三個類似的子產品可以調用，那就描述出來這個子子產品如下：
module sequential_com(
input clk,
input in1,
input in0,
input sel,
output q
);
wire in_sel;
assign in_sel = sel ? in1 : in0;
reg q_mid = 0;
always@(posedge clk) begin
q_mid <= in_sel;
end
assign q = q_mid;
endmodule 例化該子子產品得到頂層設計：
module top_module (
input [2:0] SW, // R
input [1:0] KEY, // L and clk
output [2:0] LEDR); // Q
sequential_com isnt0(
.clk(KEY[0]),
.in1(SW[0]),
.in0(LEDR[2]),
.sel(KEY[1]),
.q(LEDR[0])
);
sequential_com isnt1(
.clk(KEY[0]),
.in1(SW[1]),
.in0(LEDR[0]),
.sel(KEY[1]),
.q(LEDR[1])
);
sequential_com isnt2(
.clk(KEY[0]),
.in1(SW[2]),
.in0(LEDR[1]^LEDR[2]),
.sel(KEY[1]),
.q(LEDR[2])
);
endmodule Build a 32-bit Galois LFSR with taps at bit positions 32, 22, 2, and 1.
第一題就寫了5 bit的LFSR，這一題隻不過多了幾位，且告訴你抽頭在32, 22, 2, and 1，這幾個位置，請設計電路？
如何做這個題目呢？
其實很簡單，先寫一個位數少的，找下規律，就可以了：
module top_module(
input clk,
input reset, // Active-high synchronous reset to 32'h1
output [31:0] q
);
reg [31:0] q1;
always@(posedge clk) begin
if(reset) q1 <= 32'h1;
else begin
q1 <= {q1[0],q1[31:23],q1[0]^q1[22],q1[21:3],q1[0]^q1[2],q1[0]^q1[1]};
end
end
assign q = q1;
endmodule