LED FPGA 扫描程序

LED

LED FPGA 扫描程序

module LED_SCAN(

input wire clk_100,

input wire nReset,

output	reg [1:0]	LED_CS,
input	wire		Start,
input	wire [(D_LENGTH-1):0]	Hdata,
input	wire [(D_LENGTH-1):0]	Ldata,
//74HC595
output	reg 		nSRCLR, //clear data reg
output	reg 		nG,     //nOE 
output	reg 		RCK,    //data lock
output	reg 		SRCK,   //data clk
output	wire		SER0    //data out
           

);

parameter D_LENGTH = 8;

//===============================================================

parameter STATE_IDLE = 4’b0001;

parameter STATE_LOCK = 4’b0010;

parameter STATE_DATA = 4’b0100;

parameter STATE_SET = 4’b1000;

parameter STATE_TIMES_LOCK = 12’d8;

parameter STATE_TIMES_DATA = STATE_TIMES_LOCK + D_LENGTH;

parameter STATE_TIMES_SET = STATE_TIMES_DATA + 12’d8;

parameter STATE_TIMES_MAX = 12’d500;//STATE_TIMES_SET + 8’d2;

parameter TIME_595_SRCK = STATE_TIMES_DATA + 12’d4;

parameter TIME_165_nLOAD = 12’d4;

parameter FLITER_NUM = 8’d13; //1ms = 76us * 13

//===============================================================

reg[3:0] state;

reg[11:0] state_cnt;

wire clk_1M;

wire clk_1M_posedge;

wire clk_1M_negedge;

//===============================================================

clk_div clks

(

.sys_clk (clk_100), //100M

.nRst (nReset),

.clk_1M				(clk_1M),
.clk_1M_posedge		(clk_1M_posedge),
.clk_1M_negedge		(clk_1M_negedge)
           

);

//===============================================================

reg Start_d1;

reg Start_d2;

always@(posedge clk_100)

begin

if(!nReset)begin

Start_d1 <= 1’b0;

Start_d2 <= 1’b0;

end else begin

Start_d1 <= Start;

Start_d2 <= Start_d1;

end

end

//===============================================================

always@(posedge clk_100)

begin

if(!nReset)begin

state_cnt <= 12’d0;

// end else if(Start_d11’b0 && Start_d21’b1)begin //falling

// state_cnt <= 8’d0;

end else if(clk_1M_posedge && state_cnt < STATE_TIMES_MAX)begin

state_cnt <= state_cnt + 1’b1;

end else if(clk_1M_posedge)begin

state_cnt <= 12’d0;

end

end

//===============================================================

always@(posedge clk_100)

begin

if(!nReset)begin

state <= STATE_IDLE;

end else if(clk_1M_negedge)begin

case (state)

STATE_IDLE:

begin

if(state_cnt == 8’d1)begin

state <= STATE_LOCK;

end

end

STATE_LOCK:

begin

if(state_cnt == STATE_TIMES_LOCK)begin

state <= STATE_DATA;

end

end

STATE_DATA:

begin

if(state_cnt == STATE_TIMES_DATA)begin

state <= STATE_SET;

end

end

STATE_SET:

begin

if(state_cnt == STATE_TIMES_SET)begin

state <= STATE_IDLE;

end

end

default:

begin

state <= STATE_IDLE;

end

endcase

end

end

//===============================================================

//TPIC6A595

reg[(D_LENGTH-1):0] shift_595reg;

assign SER0 = (state == STATE_DATA)? shift_595reg[(D_LENGTH-1)] : 1’b0;

//===============================================================

always@(posedge clk_100)

begin

if(!nReset)begin

nSRCLR <= 1’b0;

end else if(state == STATE_IDLE)begin

nSRCLR <= 1’b0;

end else begin

nSRCLR <= 1’b1;

end

end

//===============================================================

always@(posedge clk_100)

begin

if(!nReset)begin

nG <= 1’b1;

end else if(state_cnt == STATE_TIMES_MAX)begin

nG <= 1’b0;

end

end

//===============================================================

reg RCK_d1;

//===============================================================

always@(posedge clk_100)

begin

if(!nReset)begin

RCK <= 1’b0;

end else if(clk_1M_negedge && state_cnt==TIME_595_SRCK)begin

RCK <= 1’b1;

end else if(clk_1M_negedge)begin

RCK <= 1’b0;

end

end

//===============================================================

always@(posedge clk_100)

begin

if(!nReset)begin

LED_CS<=2’b01;

RCK_d1 <= 1’b0;

end else begin

RCK_d1 <= RCK;

if(RCK_d11’b0 && RCK1’b1)begin

LED_CS[0] <= LED_CS[1];

LED_CS[1] <= LED_CS[0];

end

end

end

//===============================================================

always@(posedge clk_100)

begin

if(!nReset)begin

SRCK <= 1’b0;

end else if(state == STATE_DATA)begin

SRCK <= clk_1M;

end else begin

SRCK <= 1’b0;

end

end

//===============================================================

always@(posedge clk_100)

begin

if(!nReset)begin

shift_595reg <= 0;

end else if(clk_1M_negedge && state_cnt == 8’d1 && LED_CS2’b10)begin

shift_595reg <= Ldata;

end else if(clk_1M_negedge && state_cnt == 8’d1 && LED_CS2’b01)begin

shift_595reg <= Hdata;

end else if(clk_1M_negedge && state == STATE_DATA)begin

shift_595reg[(D_LENGTH-1):1] <= shift_595reg[(D_LENGTH-2):0];

shift_595reg[0] <= shift_595reg[(D_LENGTH-1)];

end

end

//===============================================================

endmodule