risc-v 文档翻译：CSR 访问顺序（CSR Access Ordering）

前言

这部分在非特权级 9.1 节的 CSR Access Ordering 部分，我们开始吧。

CSR Access Ordering

在给定的 hart 上，显式和隐式 CSR 访问按照程序顺序（program order）执行，这些指令的执行行为受所访问 CSR 的状态影响。特别地，CSR 访问会发生在任何先前的（程序序）会修改或者被这些 CSR 访问修改的指令之后，会发生在任何之后的（程序序）会修改或者被这些 CSR 访问修改的指令之前。此外，CSR读访问指令在指令执行之前返回访问的CSR状态，而CSR写访问指令在指令执行之后更新访问的CSR状态。

On a given hart, explicit and implicit CSR access are performed in program order with respect to those instructions whose execution behavior is affected by the state of the accessed CSR. In particular, a CSR access is performed after the execution of any prior instructions in program order whose behavior modifies or is modified by the CSR state and before the execution of any subsequent instructions in program order whose behavior modifies or is modified by the CSR state. Furthermore, a CSR read access instruction returns the accessed CSR state before the execution of the instruction, while a CSR write access instruction updates the accessed CSR state after the execution of the instruction.

在上述程序顺序不成立的情况下，CSR 访问是弱排序的，本地 hart 或其他 hart 可能以不同于程序顺序的顺序观察 CSR 访问。此外，CSR 访问相对于显式内存访问没有排序，除非 CSR 访问修改了执行显式内存访问的指令的执行行为，或者除非 CSR 访问和显式内存访问按定义的语法依赖项排序由本手册第 II 卷中的 Memory-Ordering PMA 部分定义的内存模型或排序要求。为了在所有其他情况下强制排序，软件应在相关访问之间执行 FENCE 指令。就 FENCE 指令而言，CSR 读访问被归类为设备输入 (I)，CSR 写访问被归类为设备输出 (O)。

Where the above program order does not hold, CSR accesses are weakly ordered, and the local hart or other harts may observe the CSR accesses in an order different from program order. In addition, CSR accesses are not ordered with respect to explicit memory accesses, unless a CSR access modifies the execution behavior of the instruction that performs the explicit memory access or unless a CSR access and an explicit memory access are ordered by either the syntactic dependencies defined by the memory model or the ordering requirements defined by the Memory-Ordering PMAs section in Volume II of this manual. To enforce ordering in all other cases, software should execute a FENCE instruction between the relevant accesses. For the purposes of the FENCE instruction, CSR read accesses are classified as device input (I), and CSR write accesses are classified as device output (O).

非正式地，CSR空间作为一个弱有序的内存映射I/O区域，在本手册第二卷的 Memory-Ordering PMAs 部分中定义。因此，CSR访问相对于所有其他访问的顺序受到与约束该区域的 MMIO （内存映射）访问顺序相同的约束。施加这些CSR排序约束主要是为了支持对主存和内存映射I/O访问进行排序，从而读取 time CSR的数据。除time, cycle, 和 mcycle CSR外，本规范第一卷和第二卷中迄今定义的csr不能直接用于其他hart或设备，也不会对其他hart或设备产生可见的副作用。因此，对上述三个以外的csr的访问可以根据FENCE指令自由地重新排序，而不会违反本规范。

Informally, the CSR space acts as a weakly ordered memory-mapped I/O region, as defined by the Memory-Ordering PMAs section in Volume II of this manual. As a result, the order of CSR accesses with respect to all other accesses is constrained by the same mechanisms that constrain the order of memory-mapped I/O accesses to such a region. These CSR-ordering constraints are imposed primarily to support ordering main memory and memory-mapped I/O accesses with respect to reads of the time CSR. With the exception of the time, cycle, and mcycle CSRs, the CSRs defined thus far in Volumes I and II of this specification are not directly accessible to other harts or devices and cause no side effects visible to other harts or devices. Thus, accesses to CSRs other than the aforementioned three can be freely reordered with respect to FENCE instructions without violating this specification.

对于引起副作用的CSR访问，上述排序约束适用于这些副作用的启动顺序，但不一定适用于这些副作用的完成顺序。硬件平台可以定义对某些csr的访问是强有序的，如本手册第二卷中内存有序pma一节所定义的那样。与访问弱有序csr和访问内存映射的I/O区域相比，访问强有序csr有更强的排序约束。

For CSR accesses that cause side effects, the above ordering constraints apply to the order of the initiation of those side effects but does not necessarily apply to the order of the completion of those side effects. The hardware platform may define that accesses to certain CSRs are strongly ordered, as defined by the Memory-Ordering PMAs section in Volume II of this manual. Accesses to strongly ordered CSRs have stronger ordering constraints with respect to accesses to both weakly ordered CSRs and accesses to memory-mapped I/O regions.