DES加密的verilog代码

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date:    14:36:27 06/21/2009 
// Design Name: 
// Module Name:    DESencode 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//
module DESencode(clk,datain,key,code);
input clk; //系统时钟信号
input [1:64]key; //密钥
input [1:64]datain; //要加密的数据
output [1:64]code; //加密后的密码
reg [1:64]code;
reg [4:1]cycnum; //用于记录循环的次数
reg [1:64]LR_reg;
reg [1:64]LR_temp;
wire [1:64]LR;
wire [1:48]bit48;
wire [1:32]bit32;
wire [1:48]sub;
wire [1:32]R_temp;
always@(negedge clk)
begin
cycnum=cycnum+1; //每个时钟周期循环次数加1
LR_temp=LR_reg;
LR_reg[1:32]=LR_temp[33:64]; //右边寄存器的值作为下一次左边寄存器的值
LR_reg[33:64]=LR_temp[1:32]^R_temp; //左边寄存器的值摩尔加置换运算P的结果作为下一次循环右边寄存器的值
end
always@(LR)
begin
LR_reg=LR; //将初始IP变换的值存入左右寄存器中
cycnum=4'h0; //同时循环的次数置0
end
IPexchange M1(.data(datain),.out64(LR)); //初始换位IP
Eexpand M2(.bit32(LR_reg[33:64]),.bit48(bit48)); //选择扩展运算E
subkey M3(.datain(key),.cycnum(cycnum),.key(sub)); //子密钥生成模块
Scompress M4(.bit48(bit48^sub),.bit32(bit32)); //选择压缩运算S
Pexchange M5(.inbit(bit32),.outbit(R_temp)); //置位运算P
IP_inverse_exchange M6(.in64(LR_reg),.cycnum(cycnum),.out64(code)); //逆变换IP_inverse
 
endmodule