MSM TLMM pinmuxcontroller
Qualcomm MSMintegrates a GPIO and Pin mux/config hardware, (TOP Level Mode
Multiplexer in shortTLMM). It controls the input/output settings on the
available pads/pinsand also provides ability to multiplex and configure the
output of variouson-chip controllers onto these pads. The pins are also of
different types,encapsulating different functions and having differing register
semantics.
Required Properties:
- compatible: should be one of the following.
- "qcom,msm-tlmm-v3": for MSM withTLMM version 3.
- "qcom,msm-tlmm-v4": for MSM withTLMM version 4.
- reg: Base address of the pin controllerhardware module and length of
the address space it occupies.
- Pin types as childnodes: Pin types supported by a particular controller
instance are represented as child nodes ofthe controller node. Each
pin type node must contain followingproperties:
Required Properties
- qcom,pin-type-*: identifies the pin type.Pin types supported are
qcom,pin-type-gp: General purpose
qcom,pin-type-sdc: SDC
- #qcom,pin-cells: number of cells in thepin type specifier.
- qcom,num-pins: number of pins of giventype present on the MSM.
Optional: A pintype may support gpiooperations. In that case, a pintype
node can have an additional child noderepresenting a gpio controller.
Additionally the pintype may also supportusing pins as interrupt triggers.
In this case we augment the gpio controllernode with interrupt controller
attributes. The interrupt controller node,if present, needs to specify the
number of pins that can be used asinterrupts as well as the id of the
processor core to which they need to berouted. Generally the apps id is
fixed for a given TLMM block in all SOCsthat use that TLMM block.
However in some SOCs, the processor id canchange. Override the default
value in that case.
- #gpio-controller: Can be used as a gpiocontroller
- #gpio-cells: Should be two. The first cellis the pin number and the
second cell is used tospecify optional parameters
- #interrupt-controller: Can be used as aninterrupt controller
- compatible: identifies the interruptcontroller feature version.
-"qcom,msm-tlmmv3-gp-intc": TLMM V3 interrupt chip.
-"qcom,msm-tlmmv4-gp-intc": TLMM V4 interrupt chip.
- num_irqs: number of pins that can be usedas an interrupt source.
- apps_id: if present, override the defaultcore id for given TLMM block.
- #interrupt-cells: Should be two. The firstcell is the pin number used as
irq and the second cellis used to specify optional
flags
- Pin groups aschild nodes: The pin mux (selecting pin function
mode) and pin config (pull up/down, driverstrength, direction) settings are
represented as child nodes of thepin-controller node. There is no limit on
the count of these child nodes.
Required Properties
-qcom,pins: phandle specifyingpin type and a pin number.
-qcom,num-grp-pins: number of pins in thegroup.
-label: name to identify the pin group tobe used by a client.
Optional Properties
-qcom,pin-func: function setting for thepin group.
The child node should contain a list ofpin(s) on which a particular pin
function selection or pin configuration (orboth) have to applied. This
list of pins is specified using the propertyname "qcom,pins". There
should be atleast one pin specified for thisproperty and there is no upper
limit on the count of pins that can bespecified. The pins are specified
using the pintype phandle and the pin numberwithin that pintype.
The pin function selection that should beapplied on the pins listed in the
child node is specified using the"qcom,pin-func" property. The value
of this property that should be applied toeach of the pins listed in the
"qcom,pins" property, should bepicked from the hardware manual of the SoC.
This property is optional in the child node ifno specific function
76 selection is desired for the pins listed in the child node or if the pinis
77 tobe used for bit banging.
78
79 Thepin group node must additionally have a pin configuration node as its own
80 child node. There can be more then one such configuration node for a pingroup
81 node. There can be one or more configurations within the configuration
82 node. These configurations are applied to all pins mentioned above usingthe
83 "qcom,pins" property. These configurations are specific to thepintype of the
84 pins.
85
86 Forthe pin configuration properties supported by both pin types lookup
87 Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
88
89 Thevalues specified by these config properties should be derived from the
90 hardware manual and these values are programmed as-is into the pinconfig
91 register of the pin-controller.
92
93 NOTE: A pin group node should be formed for all pins that are going tohave
94 thesame function and configuration settings. If a subset of pins to be used
95 bya client require different function or configuration settings or both
96 then they should be modelled as a separate pin group node to be used by
97 theclient.
98
99 Theclient nodes that require a particular pin function selection and/or
100 pin configuration should use the bindingslisted in the "pinctrl-bindings txt"
101 file.
102
103 For TLMMv3, in case of SDC pintype, we modelit as containing 6 pins. 3 each
104 for SDC1 and SDC2. Pins 0-2 corresponds toclock, data and command lines of
105 SDC1 and Pins 3-5 correspond to clock, dataand command lines of SDC2.
106
107 Example 1: A pin-controller node with pintypes
108
109 [email protected] {
110 compatible ="qcom,msm-tlmm-v3";
111 reg = <0xfd51100000x4000>;
112
113
114 gp: gp {
115 qcom,pin-type-gp;
116 qcom,num-pins =<117>;
117 #qcom,pin-cells =<1>;
118
119 msm_gpio: msm_gpio {
120 #gpio-controller;
121 #gpio-cells =<2>;
122 compatible ="msm_tlmm_v3_gpio";
123 #interrupt-controller;
124 #interrupt-cells <2>;
125 num_irqs =<117>;
126 apps_id =<4>;
127 };
128 };
129
130 sdc: sdc {
131 qcom,pin-type-sdc;
132 qcom,num-pins =<6>;
133 #qcom,pin-cells =<1>;
134 };
135 };
136
137 Example 2: Spipin entries within the pincontroller node
138 [email protected] {
139 ....
140 ..
141 pmx-spi-bus {
142
147 qcom,pins =<&gp 0>, <&gp 1>, <&gp 3>;
148 qcom,num-grp-pins =<3>;
149 qcom,pin-func =<1>;
150 label ="spi-bus";
151
152
153 spi-bus-active:spi-bus-active {
154
158 drive-strength= <8>;
159 bias-disable;
160 };
161
162 spi-bus-sleep:spi-bus-sleep {
163
167 drive-strength= <2>;
168 bias-disable;
169 };
170 };
171
172 pmx-spi-cs {
173
178 qcom,pins =<&gp 2>;
179 qcom,num-grp-pins =<1>;
180 qcom,pin-func =<1>;
181 label ="spi-cs"
182
183
184 spi-cs-active:spi-cs-active {
185
189 drive-strength= <4>;
190 bias-disable;
191 };
192
193 spi-cs-sleep:spi-cs-sleep {
194
198 drive-strength= <2>;
199 bias-disable =<0>;
200 };
201 };
202 };
203
204 Example 3: Samepin group with different pin function settings modelled as
205 separate nodes
206 [email protected] {
207 ...
208 ..
209 pmx-wcnss-5wire-active {
210 qcom,pins =<&gp 40>, <&gp 41>, <&gp 42>, <&gp 43>.
211 <&gp 44>;
212 qcom,pin-func =<1>;
213 qcom,num-grp-pins =<5>;
214 label ="wcnss-5wire-active";
215 wcnss-5wire-active:wcnss-active {
216 drive-strength= <6>; / * 6MA */
217 bias-pull-up;
218 };
219 };
220 pmx-wcnss-5wire-suspend {
221 qcom,pins =<&gp 40>, <&gp 41>, <&gp 42>, <&gp 43>.
222 <&gp 44>;
223 qcom,pin-func =<0>;
224 qcom,num-grp-pins =<5>;
225 label ="wcnss-5wire-suspend";
226 wcnss-5wire-sleep:wcnss-sleep {
227 drive-strength= <6>; / * 6MA */
228 bias-pull-down;
229 };
230 };
231 };
232
233 Example 4: SDCpins
234
235 [email protected] {
236 ...
237 ..
238 pmx-sdc1_clk {
239 qcom,pins =<&sdc 0>;
240 qcom,num-grp-pins =<1>;
241 label ="sdc1-clk";
242 sdc1_clk_on: clk_on {
243 bias-disable;
244 drive-strength= <12>;
245 };
246 sdc1_clk_off: clk_off{
247 bias-disable;
248 drive-strength= <2>;
249 };
250 };
251 pmx-sdc1_cmd {
252 qcom,pins =<&sdc 1>;
253 qcom,num-grp-pins =<1>;
254 label ="sdc1-cmd";
255 sdc1_cmd_on: clk_on {
256 bias-disable;
257 drive-strength= <12>;
258 };
259 sdc1_cmd_off: cmd_off{
260 bias-pull-up =<0x3>;
261 drive-strength= <2>;
262 };
263 };
264 pmx-sdc1_data {
265 qcom,pins =<&sdc 2>;
266 qcom,num-grp-pins =<1>;
267 label ="sdc1-data";
268 sdc1_data_on: data_on{
269 bias-pull-up;
270 drive-strength= <12>;
271 };
272 sdc1_data_off:data_off {
273 bias-pull-up;
274 drive-strength= <0>;
275 };
276 };
277 pmx-sdc2_clk {
278 qcom,pins =<&sdc 3>;
279 qcom,num-grp-pins =<1>;
280 label ="sdc2-clk";
281 sdc2_clk_on: clk_on {
282 bias-disable;
283 drive-strength= <12>;
284 };
285 sdc2_clk_off: clk_off{
286 bias-disable;
287 drive-strength= <2>;
288 };
289 };
290 pmx-sdc2_cmd {
291 qcom,pins =<&sdc 4>;
292 qcom,num-grp-pins =<1>;
293 label ="sdc2-cmd";
294 sdc2_cmd_on: cmd_on {
295 bias-disable;
296 drive-strength= <12>;
297 };
298 sdc2_cmd_off: cmd_off{
299 bias-pull-up;
300 drive-strength= <2>;
301 };
302 };
303 pmx-sdc2_data {
304 qcom,pins =<&sdc 5>;
305 qcom,num-grp-pins =<1>;
306 label ="sdc2-data";
307 sdc2_data_on: data_on{
308 bias-pull-up;
309 drive-strength= <12>;
310 };
311 sdc2_data_off:data_off {
312 bias-pull-up;
313 drive-strength= <2>;
314 };
315 };
316
317 Example 5: A SPIclient node that supports 'active' and 'sleep' states.
318
319 spi_0: [email protected] {
320 .....
321 ...
322
323 pinctrl-names ="default", "sleep";
324 pinctrl-0 =<&spi-bus-active &spi-cs-active>;
325 pinctrl-1 =<&spi-bus-sleep &spi-cs-sleep>;
326 ...
327 ..
328 };
329
330 Example 6: Awcnss node with active and sleep states
331
332 qcom,[email protected] {
333 ....
334 ..
335
336 pinctrl-names ="default", "sleep";
337 pinctrl-0 =<&wcnss-5wire-active>;
338 pinctrl-1 =<&wcnss-5wire-sleep>;
339 ...
340 };
341
342 Example 7: SDC1and SDC2 nodes with on and off states.
343
344 &sdhc_1 {
345 ....
346 ..
347
348 pinctrl-names ="on", "off";
349 pinctrl-0 =<&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
350 pinctrl-1 =<&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
351 ...
352 ..
353 };
354
355 &sdhc_2 {
356 ....
357 ..
358 pinctrl-names ="on", "off";
359 pinctrl-0 =<&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
360 pinctrl-1 =<&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
361 };
362
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