上一节PCIe功耗控制–Legacy PCI Compatible PM
讲了软件参与的功耗控制（OSPM），本次讲PCIe引入的硬件自动功耗控制。
ASPM
Active State Power Management (ASPM)是只有在D0下才可以实施的硬件自动功耗控制，其进出过程都是由硬件自动触发，软件只能使能或关闭该功能，而无法介入控制过程。ASPM定义了2个低功耗状态
-
L0s (standby state) — This state provide substantial power savings but still
allows quick entry and exit latencies. The main way this is done is by putting
the Transmitter into the Electrical Idle condition. Support for this state
was previously required for all PCIe devices in the earlier spec versions, but
in the 3.0 spec it became optional.
-
L1 ASPM — The goal for L1 is to achieve greater power conservation than
L0s for situations where longer entry and exit latencies are acceptable. For
example, in this state both Transmitters go into Electrical Idle at the same
time.
Electrical Idle
When a Transmitter’s differential signals (TxD+ and TxD‐) goes into the Electrical Idle condition, it stops signaling and instead holds its voltage very close to the common mode voltage with a differential voltage of 0 V. Signal transitions consume power, so stopping them on the Link gives power savings while still allowing a fairly quick resumption back to normal Link activity during which it is said to be in the L0 state
用一句话概括就是TX发送信号进入common_mode
TX进入electrical idle之前需要发送EIOS (Electrical Idle Ordered‐Set)，之后立马结束发送数据，并在8ns之内进入Electrical Idle。进入Electrical Idle之后至少持续20ns（各种速率都适用）。
TX退出Electrical idle必须要叫醒对端RX的CDR电路，对于Gen1因为data rate较慢，只需正常发送TS1s或者FTSs对端即可认出链路上信号幅度超过squelch threshold。对于Gen2以上的速率，则需要先发送EIEOS (Electrical Idle Exit Ordered Set)。
RX可以根据收到EIOS或者inferred Electrical idle来进入Electrical idle
RX收到EIEOC之后退出Electrical idle，CDR要重新锁定实现bit lock和block align。状态机如下
寄存器
L0s
L0s进入由TX发起的单向控制，不同设备认为链路idle的标准如下：
• Endpoint Port or Root Port:
‐ No TLPs are pending transmission or a lack of Flow Control credits
is temporarily blocking them.
‐ No DLLPs are pending transmission.
• Upstream Switch Port:
‐ The receive lane of all downstream ports are already in L0s.
‐ No TLPs are pending transmission or a lack of Flow Control credits
is temporarily blocking them.
‐ No DLLPs are pending transmission.
• Downstream Switch Port:
‐ The Switch’s Upstream Port’s Receive Lanes are in L0s.
‐ No TLPs are pending transmission or a lack of Flow Control credits
is temporarily blocking them.
‐ No DLLPs are pending for transmission
设备硬件认为链路不再idle时候就发起退出L0s，并向对端发送FTS，FTS的数量由link training时TS1/TS2中的N_FTS决定，对端RX实现bit lock and symbol lock or Block lock。
L1 ASPM
L1提供比L0s更深度的功耗节省，但是恢复也需要更长的时间。L1只能由downstream port发起，upstream port决定同意或拒绝。
spec并未规定进入L1的具体条件，只是作出如下建议
- ASPM L1 entry is supported and enabled
- Device‐specific requirements for entering L1 have been satisfied
- No TLPs are pending transmission
- No DLLPs are pending transmission
- If the downstream component is a switch, then all of the switch’s downstream ports must be in the L1 or higher power conservation state before the upstream port can initiate L1 entry.
双方协商的过程如下
- PM_ Active_State_Request_L1 DLLP — issued by the downstream port to start the negotiation process.
- PM_ Request_Ack DLLP — returned by the upstream port when all of its requirements to enter L1 ASPM have been satisfied.
- PM_Active_State_Nak message TLP — returned by the upstream port when it is unable to enter the L1 ASPM state.
一个协商成功的例子
一个协商失败的例子
与进入L1只能downstream port发起不同的是，退出L1可以由链路任意一方发起，并且不需要协商。Switch如果收到某个port退出L1的请求，此时如果其他相关port也在发送信号链路上，也需要把他们叫醒。