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X-Silicon 旨在通过其新型低功耗“C-GPU”架构解决当前边缘计算的局限性。
San Diego-based startup X-Silicon recently announced a novel RISC-V architecture that combines CPU, GPU, and NPU into a single core. The new NanoTile architecture is described as a low-power "C-GPU" that converges RISC-V vector CPU capabilities with GPU and AI/ML acceleration in a unique monolithic processor design.
X-Silicon的单核概念
X-Silicon claims that Nanotile is the first open-source architecture of its kind. It provides register-level access through the Hardware Abstraction Layer (HAL), allowing OEMs and content providers to customize their drivers and applications for broad hardware adaptability.
NanoTile 架构之下
The key to this architecture lies in its multi-core design, where multiple C-GPU cores are arranged on a single chip and linked by an on-chip fast synthesizer structure. This setup dynamically aggregates the output of each core into a common buffer, enhancing data processing for graphics, video processing, and AI tasks. Compute RAM (C-RAM) is located close to the processing core and unified memory architecture, which significantly reduces latency and improves overall computing efficiency.
X-Silicon says its technology can address the limitations faced by existing GPUs. GPUs that were originally designed for gaming are now grappling with new, diverse workloads such as artificial intelligence and parallel computing. Traditional GPU architectures are often inefficient due to fixed-function processing units and underutilization in non-gaming applications.
In contrast, X-Silicon's C-GPUs are designed to optimize performance across a wider range of applications by adopting a scalable, tile-based approach to efficient rendering and management of compute.
RISC-V CPU-GPU 混合体
开源 RISC-V CPU-GPU 混合体在计算行业前景广阔。
By integrating CPU and GPU functions into a single RISC-V-based processor, NanoTile simplifies the hardware stack and reduces power consumption, making it suitable for applications in energy-sensitive environments such as mobile devices and embedded systems. The unified architecture also improves performance by minimizing the latency typically associated with communication between separate CPU and GPU chips.
X-Silicon的单核架构
The RISC-V ISA ensures a high degree of modularity and scalability, allowing users to tailor hybrid processors to specific applications. By offering the RISC-V CPU/GPU hybrid architecture under an open-source license, X-Silicon facilitates a collaborative environment where developers, engineers, and researchers can contribute to and enhance the design of the processor. This openness allows the wider community to experiment and refine the technology, leading to faster progress and wider applications. As a result, X-Silicon's open-source RISC-V CPU/GPU hybrid can lead to more personalized and efficient computing solutions.
Flexibility across industries
With 14 patents to support its novel design, X-Silicon hopes that its architecture will transform edge computing with the massive parallelism of RISC-V that integrates AI/ML and graphics capabilities. The company plans to deliver new solutions to a wide range of industries, including wearable technology, AR/VR headsets, automotive displays, and more.
The impact of RISC-V on technology and innovation
The RISC-V standard is not a competitive advantage in itself, the competition lies in the implementation part. Just like USB, Ethernet, and Bluetooth, among others, RISC-V ISA is a publicly available standard that allows anyone to build their own solution based on the RISC-V standard. RISC-V supports a wide ecosystem, both open and private, giving developers the freedom to create custom solutions for specific scenarios. Today, RISC-V continues to grow substantially. RISC-V has become the most prosperous and globally adopted non-proprietary ISA standard in history. More than 13 billion RISC-V cores are on the market. According to an analysis by SHD Group, RISC-V SoC unit shipments are expected to surge to 16.2 billion units, with revenue reaching $92 billion by 2030.
RISC-V has received support from the global community. The community collaborates on technology standards, drives innovation, and fosters a diverse ecosystem. The global community has contributed publicly available IPs to create a shared set of extensions that can be used with the underlying ISA. All extensions are open and publicly available. Open collaboration enables companies and developers to work together, share ideas, and contribute to the development of the ISA and related extensions. In addition, RISC-V is a standard, not open source. RISC-V ISA and extensions go through a robust community governance process to be approved and frozen. With this modular approach of freezing standard ISAs and extensions, innovation can be achieved while preventing fragmentation.
An open review of standards can improve the robustness and resilience of cybersecurity. RISC-V's openness fosters competition and encourages investment in new technologies. By allowing design freedom, RISC-V offers innovation potential for everyone. Because other architectures use a private licensing model that restricts innovation, no other architecture can give this potential.
Today, more and more countries and regions are investing in RISC-V as a way to build and grow the digital economy. RISC-V has become the foundation of the European Processor Initiative. The European Commission has provided substantial funding under the European Chips Act. At the same time, the EU conducts research on the importance of open software and hardware. The EU invests in design capabilities for high-performance processing and new industry partnerships such as Quintauris. RISC-V is funded by American University Labs to contribute to the public domain standards ISA. The momentum of RISC-V in the U.S. continues as many multinational corporations, universities, government agencies, start-ups, venture capital firms, and others adopt and invest heavily in RISC-V. Industry, research, and academia in China have also contributed to the overall success of RISC-V, including many areas of global collaboration.
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