1 AXI4 Interface Block Memory Generator的使用
I've been reading axi's memory for a long time, so I should write one myself, and find the source code of the relevant code and simulation.
https://blog.csdn.net/liuhandd/article/details/115001224 this is an example, I create a new project on my computer, study/project_1 actually do it
After instantiating this IP, wait a while for it to finish synthesizing itself. Right-click to open the example design.
在新的example design的工程界面下，可以点击RTL ANALYSIS-->open elaborated design看到schematic。
2 Non-aligned operations
https://jishuin.proginn.com/p/763bfbd293ac
Compilers tend to place variables on even-numbered addresses aligned with their size based on their size
For example, if we don't give us specific instructions, the compiler will tend to:
Align uint32_t (4 bytes) to a 4-byte address, 0x0, 0x4, 0x8, 0xC... , which is what we often call Word Aligned;
Align the uint16_t (2 bytes) to the 2-byte address, 0x0, 0x2, 0x4... This is what we often call Half-word Aligned;
Align uint64_t (8 bytes) to 8 bytes, 0x0, 0x8... This is what we often call Double Word Aligned;
3 DDR IP
The DDR3 IP can choose whether to have a controller or not, but it must be with a PHY, and the PHY is a hard core. Pay attention to the manual.
Articles I checked:
1. Controller unit: including input command analysis, mode configuration & control part;
2. Line address gating unit: the line activation is operated through here;
3. Bank control logic: bank/column address decoding is used to bank gating
4. The column address selection unit, the read and write operation is sent to 1 when the column address is opened at the same time;
5. Latch and control logic: refresh and pre-charge the module;
6. Internal storage array, which is divided into 8 banks, each bank is divided into 16384 rows and 128 columns;
7. Read/write data caching and interface driver; DQ data interacts with each other inside and outside after changing the bit width;
DDR Basic Steps:
启动：上电-＞解复位-＞初始化-＞ZQCL-＞LEVELING-＞IDLE（READY）
Read: IDLE - > Row Activation - > Read Data (1 or more bursts) - > Precharge - > IDLE
Write: IDLE - > Row Activation - > Write Data (1 or more bursts) - > Precharge - > IDLE
刷新：IDLE-＞REF-＞IDLE
Self-refreshed entry and exit: IDLE->SFR->IDLE
Periodic calibration: IDLE—>ZQCS—>IDLE, generally operated when external temperature or voltage changes
动态更改配置：IDLE-＞MRS／MPR-＞IDLE
4 OCM
When using OCM in zynq, how can I remap OCM to high-level address 0xfffc0000-0xfffffe00, after I set up the mapped address, the ARM test will go into an endless loop
I checked:
CPU0 and CPU1 run their own programs. In this article, we need to enable communication between the two CPUs, and the data can be transmitted using DDR or OCM (on chip memory). OCM is a single-port storage space, but you can use the ZynqSoC's DMA to access OCM's other switching resources in parallel to simulate a dual-port storage space. To implement this mechanism, access must be 128-bit data aligned, which must be met in any case. This method can achieve high throughput, because DMA can efficiently transfer large amounts of data.
The OCM is 256KB and is divided into 4 blocks according to 64KB, of which the first three blocks are expressed in the SDK as RAM0, which occupies 192KB and is at the beginning of the address space and DDR shared address space, and the last block is 64KB at the end of the address space. OCM can be organized into 128-bit word storage space, and the OCM storage space can be divided into four 64k byte storage areas in different locations according to the address space defined in the PS section. The initial configuration is to map the first three 64K byte blocks to the address space at the beginning of the PS section, and the last 64K byte block to the address space at the end of the PS section
When ZYNQ curing, DDR is normally required to participate, but sometimes when hardware design, DDR may be removed or design errors, which will cause ZYNQ to fail to solidify normally, I have written an article that uses static link libraries for DDR curing, at that time, it was compressed FSBL related code and only retained the function in FLASH mode, for other modes may not be able to use normally, this article will further introduce the situation without DDR curing, explain how to modify FSBL to achieve ZYNQ's program curing, and give a demo for demonstration testing。
5 failfast
用于查询failfast的design utilities是在tool->Vivado store 或者tcl store安装
Failfast is a good report
https://www.likecs.com/show-44843.html
平台:Vivado16.4
Project: EADCH_2.3.0_Beta
According to the design process in the UltraFast Design Methodology Timing Closure Quick Reference Guide (UG1292), the first stage is the "Initial Design Flow Check", which mainly reads the report generated by three operations, which are:
report_failfast
report_timing_summary
report_methodology
report_failfast the project report generated, see which items are REVIEW, and then check what each item means, the possible causes, the recommended optimization methods, etc., from UG949, and try again and again until the result is acceptable.
Bibliography:
UG949
UG1292