Mr. High Speed member - Huang Gang
The importance of transmission line impedance control to system performance cannot be overstated, and every PCB fabrication fab is working towards the goal of being able to control tighter impedance tolerances. But we also know that the control tolerance of the impedance of the transmission line will actually be affected by the factors of the PCB structure itself, just like the following slice diagram of the PCB differential line, there are at least 6 or 7 parameters that affect the impedance of the transmission line, such as line width, line spacing, upper dielectric thickness, lower dielectric thickness, copper thickness, dielectric constant of the plate, etc. Together, they determine the impedance of this pair of differential lines, and their control tolerances determine the tolerance of the impedance of the differential lines!
Today, Mr. High-speed wants to take a high-end route in this article, let's study all the parameters mentioned above that affect the impedance of the transmission line, whether we can compare the quantitative order for them, and see which factor has the greatest impact on the tolerance of the impedance of the processed transmission line. Is this an interesting research direction?
Let's take a look at the case of the test board recently made by Mr. High Speed, what we did is a USB test fixture, and the PCB design is as follows:
In order to ensure high-frequency performance, we use a 1 to 2 laser hole process, and then the traces are in the L2 layer. Because the thickness of the board is relatively thin, that is, the thickness of the upper and lower layers of the L2 layer is also very thin, so the line width of our L2 layer is naturally designed to be very thin.
The line width and line spacing of the stack and L2 layer are as follows. The thickness of the upper and lower layers is more than 3mil, and the line width is more than 3mil when the differential impedance is controlled at 85 ohms. By the way, the plate is a medium-loss plate with a dielectric constant of around 3.8.
However, we also know that there must be deviations in impedance processing, and the plate factory generally guarantees a 10% impedance deviation, which may be 8% impedance deviation strictly. The figure below shows the results of the transmission line for the impedance test after the final processing of the project.
In fact, it can be seen that the impedance of the long and short wires on the same board is very good to meet the impedance deviation of 8% (in fact, it is close to 5%), and the impedance of this group of differential lines has actually been processed very well!
So let's go back to the theoretical analysis. According to the stack given by the board factory, we simulated the impedance through the simulation software, and we can indeed see that the median impedance is 85 ohms, and the following is the transmission line impedance simulation result under the condition of 2 inch wire length.
So how do we study the influence of the above parameters on the impedance? We can use the tolerance analysis control of the relevant simulation software, commonly known as DOE analysis. The main purpose of this control is to analyze the impact of each parameter on the deviation of the overall impedance result if there is a certain deviation, and at the same time, you can also get the proportion of the influence of each parameter on the subsequent results!
Let's first use a diagram of the transmission line to illustrate the parameters in this case, as follows:
According to the stack given by the board factory, the median values of each parameter are: line width W=3.4mil, line spacing S=8mil, upper dielectric thickness (plus copper thickness) H1=4.4mil, lower dielectric thickness H2=3.2mil, copper thickness T=1.2mil, and the dielectric constant of the plate DK=3.8, then we start to simulate DOE. The principle is also very simple, we set the above 6 variable parameters to allow about 10% error, let's see what is the contribution ratio of each parameter to the final impedance result after DOE simulation!
Let's take a look at the DOE simulation results in this case, which is the following figure:
First of all, the table on the left gives the proportion of the impact of the same error change of different variables on the impedance of the subsequent transmission line. For example, the error of line width W will account for about 17.5%, the dielectric constant DK will also have an effect of 15.8%, and the copper thickness T will also account for about 11.3%. There are also parameters that may affect each other, so the results are also considered. For example, the combined effect of line width W and upper medium thickness H1 is 4.3%.
This analysis is actually of great significance, it can clearly give which parameter has the greatest impact, and it may be necessary to focus on controlling this factor in the processing process, so that you can actually have a better grasp of the final impedance tolerance. In addition, it should be known that the DOE analysis results of the influence degree of each parameter must be different for different stacks and different line widths and line spacing, which may have the greatest impact on line width in project A, but may have the greatest impact on the thickness of the medium in project B. Therefore, we need to do a specific analysis of the actual situation of your product.
Finally, do you get this method?
Questions in this issue
If you use the example in the article to analyze the loss situation, which parameters do you think the loss is related to, and which parameters have the greatest impact?